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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 16-bit single-chip microcomputer m16c family / m16c/20 series user? manual M30218 group before using this material, please visit the above website to confirm that this is the most current document available. http://www.infomicom.maec.co.jp/indexe.htm rev.b revision date: jun. 27, 2001
keep safety first in your circuit designs! notes regarding these materials mitsubishi electric corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semicon- ductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or repro- duce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
preface this user's manual describes the function and features of the mitsubishi M30218 group cmos 16-bit microcomputer. the software features are explained to help designers take full advantage of the m16c functions. for details about the software, please refer to the m16c/60, m16c/20 series software manual, and for the development support tools, please refer to the related instruction manual.
how to use this manual this user's manual is written for the M30218 group. the reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers. this manual is for the use of the models below. ?m30217ma-axxxfp ?M30218mc-axxxfp ?M30218fcfp these products have similar features except for the memories, which differ from one product to another. this manual gives descriptions of M30218mc-axxxfp. memories built-in are as shown below. be careful when writing a program, as the memories have different capacities. the figure of each register configuration describes its functions, contents at reset, and attributes as follows : ?bit attribute r.....read w.....write o.....possible to read o.....possible to write x.....impossible to read x.....impossible to write bit attribute ram size (byte) 12k 1 k 512 M30218mc-axxxfp M30218fcfp 1 2 8 k rom size (byte) m 3 0 2 1 7 m a - a x x x f p 5k 9 6 k t a 1 o s t a 2 o s t a 0 o s o n e - s h o t s t a r t f l a g s y m b o la d d r e s sw h e n r e s e t o n s f0 3 8 2 1 6 0 0 x 0 0 0 0 0 2 t i m e r a 0 o n e - s h o t s t a r t f l a g timer a1 one-shot start flag t i m e r a 2 o n e - s h o t s t a r t f l a g t i m e r a 3 o n e - s h o t s t a r t f l a g t i m e r a 4 o n e - s h o t s t a r t f l a g t a 3 o s t a 4 o s b i t n a m ef u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t a 0 t g l t a 0 t g h 0 0 : i n p u t o n t a 0 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 4 o v e r f l o w i s s e l e c t e d 1 1 : t a 1 o v e r f l o w i s s e l e c t e d timer a0 event/trigger select bit b 7 b 6 n o t e : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . w h e n t a i i n i s s e l e c t e d , t a i o u t a s s i g n e d o n s a m e p i n c a n n o t b e u s e d . ( i = 0 t o 4 ) w r 1 : t i m e r s t a r t w h e n r e a d , t h e v a l u e i s 0 n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e .
this manual comprises of five chapters. use the suggested chapters as a reference for the following topics: * to understand hardware specifications ................................................... chapter 1 hardware * to understand the basic way of using peripheral features and the operation timing ................................ chapter 2 peripheral functions usage * to observe applications of peripheral features ........................ chapter 3 examples of peripheral functions applications * to understand interrupt timing in detail .................................................... chapter 4 interrupts * to understand standard data............................................ chapter 5 standard characteristics this manual includes a quick reference immediately following the table of contents, indicate the page of the topic to be pursued. * to find a page describing a specific register by the register address ............................... quick reference to pages classified by address
m16c family-related document list usages (microcomputer development flow) outline design of system selection of microcomputer detail design of system hard- ware devel- opment system evaluation soft- ware devel- opment contents hardware specifications (pin assignment, memory map, specifications of peripheral func- tions, electrical characteristics, timing charts) detailed description about hardware specifica- tions, operation, and application examples (connection with peripherals, relationship with software) method for creating programs using assembly and c languages detailed description about operation of each instruction (assembly language) hardware type of document data sheet and data book users manual software m16c family m16c/80 series m16c/80 group m16c/60 series m16c/60 group m16c/61 group m16c/62 group m16c/20 series m16c/20 group m16c/21 group m16c family line-up programming manual software manual
table of contents chapter 1 hardware ________________________________________ description .................................................................................................................... ........................2 pin description ................................................................................................................ ...................... 7 memory ......................................................................................................................... ........................9 central processing unit (cpu) .................................................................................................. ......... 12 reset .......................................................................................................................... ......................... 15 software reset ................................................................................................................. .................. 18 clock generating circuit ....................................................................................................... .............. 19 clock output ................................................................................................................... .................... 23 stop mode ...................................................................................................................... ....................23 wait mode ...................................................................................................................... ..................... 23 status transition of bclk ...................................................................................................... ............ 24 power control .................................................................................................................. ................... 25 protection ..................................................................................................................... ....................... 27 overview of interrupt .......................................................................................................... ................. 28 watchdog timer ................................................................................................................. ................. 46 dmac ........................................................................................................................... ...................... 48 fld controller ................................................................................................................. .................... 54 timer .......................................................................................................................... ......................... 71 timer a ........................................................................................................................ ....................... 72 timer b ........................................................................................................................ ....................... 82 serial i/o ..................................................................................................................... ........................ 88 serial i/o2 .................................................................................................................... ..................... 102 a-d converter .................................................................................................................. ................. 115 d-a converter .................................................................................................................. ................. 125 crc calculation circuit ........................................................................................................ ............ 127 programmable i/o ports ......................................................................................................... .......... 129 exclusive high-breakdown-voltage output ports ............................................................................. 129 flash memory ................................................................................................................... ................ 154
chapter 2 peripheral functions usage ________________________ 2.1 protect .................................................................................................................... .................... 178 2.1.1 overview ................................................................................................................. ............. 178 2.1.2 protect operation ........................................................................................................ ......... 178 2.2 timer a .................................................................................................................... ................... 180 2.2.1 overview ................................................................................................................. ............. 180 2.2.2 operation of timer a (timer mode) ...................................................................................... 18 6 2.2.3 operation of timer a (timer mode, gate function selected) ................................................. 188 2.2.4 operation of timer a (timer mode, pulse output function selected) .................................... 190 2.2.5 operation of timer a (event counter mode, reload type selected) ...................................... 192 2.2.6 operation of timer a (event counter mode, free run type selected) .................................... 194 2.2.7 operation of timer a (2-phase pulse signal process in event counter mode, normal mode se- lected) ........................................................................................................................ .......... 196 2.2.8 operation of timer a (2-phase pulse signal process in event counter mode, multiply-by-4 mode selected) ...................................................................................................................... ........ 198 2.2.9 operation of timer a (one-shot timer mode) ....................................................................... 200 2.2.10 operation of timer a (one-shot timer mode, external trigger selected) ............................. 202 2.2.11 operation of timer a (pulse width modulation mode, 16-bit pwm mode selected) .......... 204 2.2.12 operation of timer a (pulse width modulation mode, 8-bit pwm mode selected) ............ 206 2.2.13 precautions for timer a (timer mode) ................................................................................ 208 2.2.14 precautions for timer a (event counter mode) .................................................................. 209 2.2.15 precautions for timer a (one-shot timer mode) ................................................................. 210 2.2.16 precautions for timer a (pulse width modulation mode) ................................................... 211 2.3 timer b .................................................................................................................... ................... 212 2.3.1 overview ................................................................................................................. ............. 212 2.3.2 operation of timer b (timer mode) ...................................................................................... 21 6 2.3.3 operation of timer b (event counter mode) ........................................................................ 218 2.3.4 operation of timer b (pulse period measurement mode) ................................................... 220 2.3.5 operation of timer b (pulse width measurement mode) ..................................................... 222 2.3.6 precautions for timer b (timer mode, event counter mode) ................................................ 224 2.3.7 precautions for timer b (pulse period/pulse width measurement mode) ........................... 225 2.4 clock-synchronous serial i/o ............................................................................................... ...... 226 2.4.1 overview ................................................................................................................. ............. 226 2.4.2 operation of serial i/o (transmission in clock-synchronous serial i/o mode) ..................... 232 2.4.3 operation of the serial i/o (transmission in clock-synchronous serial i/o mode, transfer clock
output from multiple pins function selected) ........................................................................ 236 2.4.4 operation of serial i/o (reception in clock-synchronous serial i/o mode) ........................... 240 2.4.5 precautions for serial i/o (in clock-synchronous serial i/o) ................................................ 244 2.5 clock-asynchronous serial i/o (uart) ...................................................................................... 2 46 2.5.1 overview ................................................................................................................. .............246 2.5.2 operation of serial i/o (transmission in uart mode) ......................................................... 254 2.5.3 operation of serial i/o (reception in uart mode) .............................................................. 258 2.6 serial i/o2 ................................................................................................................ ................... 262 2.6.1 overview ................................................................................................................. .............262 2.6.2 serial i/o2 connection examples ......................................................................................... 2 67 2.6.3 serial i/o2 modes ........................................................................................................ ........ 269 2.6.4 serial i/o2 operations (transmission in 8-bit serial i/o mode) ........................................... 270 2.6.5 serial i/o2 operations (transmission/reception in automatic transfer serial i/o mode) ...... 274 2.6.6 serial i/o2 operations (transmission/reception in automatic transfer serial i/o mode, using handshake signal) .............................................................................................................. . 278 2.6.7 precautions for serial i/o2 .............................................................................................. ..... 282 2.7 fld (vfd) controller ....................................................................................................... ...........286 2.7.1 overview ................................................................................................................. .............286 2.7.2 fld operation (fld automatic display and key-scan using segments) .............................. 296 2.7.3 fld operation (fld automatic display and key-scan using digits) ...................................... 302 2.7.4 fld operation (fld display and key-scan using segment by software) ............................. 306 2.7.5 fld operation (display with digit expander m35501fp) ..................................................... 312 2.7.6 fld operation (display with digit expander m35501fp: column discrepancy) ................... 318 2.7.7 precautions for fld controller ........................................................................................... .. 325 2.8 a-d converter .............................................................................................................. ............... 326 2.8.1 overview ................................................................................................................. .............326 2.8.2 operation of a-d converter (one-shot mode) ...................................................................... 332 2.8.3 operation of a-d converter (in repeat mode) ...................................................................... 334 2.8.4 operation of a-d converter (in single sweep mode) ........................................................... 336 2.8.5 operation of a-d converter (in repeat sweep mode 0) ....................................................... 338 2.8.6 operation of a-d converter (in repeat sweep mode 1) ....................................................... 340 2.8.7 precautions for a-d converter ............................................................................................ . 342 2.8.8 method of a-d conversion (10-bit mode) ............................................................................ 343 2.8.9 method of a-d conversion (8-bit mode) .............................................................................. 345 2.8.10 absolute accuracy and differential non-linearity error .................................................... 347
2.8.11 internal equivalent circuit of analog input ......................................................................... 349 2.8.12 sensors output impedance under a-d conversion .......................................................... 350 2.9 d-a converter .............................................................................................................. ............... 352 2.9.1 overview ................................................................................................................. ............. 352 2.9.2 d-a converter operation .................................................................................................. ... 353 2.10 dmac ...................................................................................................................... ................. 354 2.10.1 overview ................................................................................................................ ............ 354 2.10.2 operation of dmac (one-shot transfer mode) ................................................................... 358 2.10.3 operation of dmac (repeated transfer mode) ................................................................... 360 2.11 crc calculation circuit ................................................................................................... ......... 362 2.11.1 overview ................................................................................................................ ............ 362 2.11.2 operation of crc calculation circuit ................................................................................ 363 2.12 watchdog timer ............................................................................................................ ........... 364 2.12.1 overview ................................................................................................................ ............ 364 2.12.2 operation of watchdog timer ............................................................................................ 3 66 2.13 address match interrupt ................................................................................................... ........ 368 2.13.1 overview ................................................................................................................ ............ 368 2.13.2 operation of address match interrupt ................................................................................ 370 2.14 power control ............................................................................................................. .............. 372 2.14.1 overview ................................................................................................................ ............ 372 2.14.2 stop mode set-up ........................................................................................................ ..... 377 2.14.3 wait mode set-up ........................................................................................................ ..... 378 2.14.4 precautions in power control ............................................................................................ 379 2.15 programmable i/o ports .................................................................................................... ....... 380 2.15.1 overview ................................................................................................................ ............ 380 chapter 3 examples of peripheral functions applications ________ 3.1 long-period timers ......................................................................................................... ....... 388 3.2 variable-period variable-duty pwm output ........................................................................... 392 3.3 delayed one-shot output .................................................................................................... .. 396 3.4 buzzer output .............................................................................................................. ........... 400 3.5 solution for external interrupt pins shortage ......................................................................... 402 3.6 memory to memory dma transfer ......................................................................................... 404 3.7 controlling power using stop mode ....................................................................................... 408 3.8 controling power using wait mode ........................................................................................ 412
chapter 4 interrupt_________________________________________ 4.1 overview of interrupt ...................................................................................................... ............408 4.1.1 type of interrupts ....................................................................................................... .......... 408 4.1.2 software interrupts ...................................................................................................... ........ 409 4.1.3 hardware interrupts ...................................................................................................... .......420 4.1.4 interrupts and interrupt vector tables ................................................................................. 42 1 4.2 interrupt control .......................................................................................................... ................ 423 4.2.1 interrupt enable flag .................................................................................................... ....... 425 4.2.2 interrupt request bit .................................................................................................... ........ 425 4.2.3 interrupt priority level select bit and processor interrupt priority level (ipl) .................... 426 4.2.4 rewrite the interrupt control register ................................................................................... . 427 4.3 interrupt sequence ......................................................................................................... ............ 428 4.3.1 interrupt response time .................................................................................................. ...428 4.3.2 variation of ipl when interrupt request is accepted .......................................................... 429 4.3.3 saving registers ......................................................................................................... .........430 4.4 returning from an interrupt routine ........................................................................................ ... 432 4.5 interrupt priority ......................................................................................................... ................. 432 4.6 multiple interrupts ........................................................................................................ ............... 434 4.7 precautions for interrupts ................................................................................................. .......... 436 chapter 5 standard characteristics ___________________________ 5.1 standard dc characteristics ................................................................................................ ......440 5.1.1 standard ports characteristics ........................................................................................... . 440 5.1.2 characteristics of icc-f(xin) ............................................................................................ ...444 5.2 standard characteristics of a-d converter ................................................................................ 44 6 5.3 standard characteristics of d-a converter ................................................................................ 44 8 5.4 standard characteristics of pull-up resistor ............................................................................. 45 1
this page kept blank for layout purposes.
quick reference to pages classified by address 0 0 4 0 1 6 0 0 4 1 1 6 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 0 0 4 c 1 6 0 0 4 d 1 6 0 0 4 e 1 6 0 0 4 f 1 6 0 0 5 0 1 6 0 0 5 1 1 6 0 0 5 2 1 6 0 0 5 3 1 6 0 0 5 4 1 6 0 0 5 5 1 6 0 0 5 6 1 6 0 0 5 7 1 6 0 0 5 8 1 6 0 0 5 9 1 6 0 0 5 a 1 6 0 0 5 b 1 6 0 0 5 c 1 6 0 0 5 d 1 6 0 0 5 e 1 6 0 0 5 f 1 6 0 3 4 0 1 6 0 3 4 1 1 6 0 3 4 2 1 6 0 3 4 3 1 6 0 3 4 4 1 6 0 3 4 5 1 6 0 3 4 6 1 6 0 3 4 7 1 6 0 3 4 8 1 6 0 3 4 9 1 6 0 3 4 a 1 6 0 3 4 b 1 6 0 3 4 c 1 6 0 3 4 d 1 6 0 3 4 e 1 6 0 3 4 f 1 6 0 3 5 0 1 6 0 3 5 1 1 6 0 3 5 2 1 6 0 3 5 3 1 6 0 3 5 4 1 6 0 3 5 5 1 6 0 3 5 6 1 6 0 3 5 7 1 6 0 3 5 8 1 6 0 3 5 9 1 6 0 3 5 a 1 6 0 3 5 b 1 6 0 3 5 c 1 6 0 3 5 d 1 6 0 3 5 e 1 6 0 3 5 f 1 6 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 i n t 1 i n t e r r u p t c o n t r o l r e g i s t e r ( i n t 1 i c ) t i m e r b 0 i n t e r r u p t c o n t r o l r e g i s t e r ( t b 0 i c ) t i m e r b 2 i n t e r r u p t c o n t r o l r e g i s t e r ( t b 2 i c ) t i m e r a 1 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 1 i c ) t i m e r a 3 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 3 i c ) u a r t 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r ( s 0 t i c ) i n t 2 i n t e r r u p t c o n t r o l r e g i s t e r ( i n t 2 i c ) i n t 0 i n t e r r u p t c o n t r o l r e g i s t e r ( i n t 0 i c ) t i m e r b 1 i n t e r r u p t c o n t r o l r e g i s t e r ( t b 1 i c ) t i m e r a 0 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 0 i c ) t i m e r a 2 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 2 i c ) t i m e r a 4 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 4 i c ) u a r t 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r ( s 0 r i c ) u a r t 1 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r ( s 1 t i c ) u a r t 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r ( s 1 r i c ) d m a 1 i n t e r r u p t c o n t r o l r e g i s t e r ( d m 1 i c ) d m a 0 i n t e r r u p t c o n t r o l r e g i s t e r ( d m 0 i c ) a - d c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e r ( a d i c ) d m a 0 c o n t r o l r e g i s t e r ( d m 0 c o n ) d m a 0 s o u r c e p o i n t e r ( s a r 0 ) d m a 0 t r a n s f e r c o u n t e r ( t c r 0 ) d m a 0 d e s t i n a t i o n p o i n t e r ( d a r 0 ) d m a 1 c o n t r o l r e g i s t e r ( d m 1 c o n ) d m a 1 s o u r c e p o i n t e r ( s a r 1 ) d m a 1 t r a n s f e r c o u n t e r ( t c r 1 ) d m a 1 d e s t i n a t i o n p o i n t e r ( d a r 1 ) w a t c h d o g t i m e r s t a r t r e g i s t e r ( w d t s ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d c ) p r o c e s s o r m o d e r e g i s t e r 0 ( p m 0 ) a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0 ( r m a d 0 ) a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1 ( r m a d 1 ) s y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( c m 0 ) s y s t e m c l o c k c o n t r o l r e g i s t e r 1 ( c m 1 ) a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r ( a i e r ) p r o t e c t r e g i s t e r ( p r c r ) p r o c e s s o r m o d e r e g i s t e r 1 ( p m 1 ) 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 4 3 5 0 5 1 5 1 5 1 5 0 5 1 5 1 5 1 4 7 1 8 2 2 4 3 2 7 4 3 3 4 5 7 5 8 5 9 a d d r e s sr e g i s t e rp a g e a d d r e s sr e g i s t e rp a g e i n t 3 i n t e r r u p t c o n t r o l r e g i s t e r ( i n t 3 i c ) i n t 4 i n t e r r u p t c o n t r o l r e g i s t e r ( i n t 4 i c ) i n t 5 i n t e r r u p t c o n t r o l r e g i s t e r ( i n t 5 i c ) 3 4 3 4 s i / o 2 a u t o m a t i c t r a n s f e r i n t e r r u p t c o n t r o l r e g i s t e r ( a s i o i c ) f l d i n t e r r u p t c o n t r o l r e g i s t e r ( f l d i c ) p 3 f l d / p o r t s w i t c h r e g i s t e r ( p 3 f p r ) p 5 d i g i t o u t p u t s e t r e g i s t e r ( p 5 d o r ) t o f f 2 t i m e s e t r e g i s t e r ( t o f f 2 ) f l d d a t a p o i n t e r ( f l d d p ) f l d o u t p u t c o n t r o l r e g i s t e r ( f l d c o n ) p 6 d i g i t o u t p u t s e t r e g i s t e r ( p 6 d o r ) p 4 f l d / p o r t s w i t c h r e g i s t e r ( p 4 f p r ) p 2 f l d / p o r t s w i t c h r e g i s t e r ( p 2 f p r ) t d i s p t i m e s e t r e g i s t e r ( t d i s p ) t o f f 1 t i m e s e t r e g i s t e r ( t o f f 1 ) f l d m o d e r e g i s t e r ( f l d m ) s e r i a l i / o 2 a u t o m a t i c t r a n s f e r d a t a p o i n t e r ( s i o 2 d p ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 ( s i o 2 c o n 1 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 ( s i o 2 c o n 2 ) s e r i a l i / o 2 r e g i s t e r / t r a n s f e r c o u n t e r ( s i o 2 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 3 ( s i o 2 c o n 3 ) 5 7 5 7 5 6 1 0 5 1 0 5 1 0 4 1 0 4 1 0 5
quick reference to pages classified by address a d d r e s sr e g i s t e rp a g ea d d r e s sr e g i s t e rp a g e 0 3 8 0 1 6 0 3 8 1 1 6 0 3 8 2 1 6 0 3 8 3 1 6 0 3 8 4 1 6 0 3 8 5 1 6 0 3 8 6 1 6 0 3 8 7 1 6 0 3 8 8 1 6 0 3 8 9 1 6 0 3 8 a 1 6 0 3 8 b 1 6 0 3 8 c 1 6 0 3 8 d 1 6 0 3 8 e 1 6 0 3 8 f 1 6 0 3 9 0 1 6 0 3 9 1 1 6 0 3 9 2 1 6 0 3 9 3 1 6 0 3 9 4 1 6 0 3 9 5 1 6 0 3 9 6 1 6 0 3 9 7 1 6 0 3 9 8 1 6 0 3 9 9 1 6 0 3 9 a 1 6 0 3 9 b 1 6 0 3 9 c 1 6 0 3 9 d 1 6 0 3 9 e 1 6 0 3 9 f 1 6 0 3 a 0 1 6 0 3 a 1 1 6 0 3 a 2 1 6 0 3 a 3 1 6 0 3 a 4 1 6 0 3 a 5 1 6 0 3 a 6 1 6 0 3 a 7 1 6 0 3 a 8 1 6 0 3 a 9 1 6 0 3 a a 1 6 0 3 a b 1 6 0 3 a c 1 6 0 3 a d 1 6 0 3 a e 1 6 0 3 a f 1 6 0 3 b 0 1 6 0 3 b 1 1 6 0 3 b 2 1 6 0 3 b 3 1 6 0 3 b 4 1 6 0 3 b 5 1 6 0 3 b 6 1 6 0 3 b 7 1 6 0 3 b 8 1 6 0 3 b 9 1 6 0 3 b a 1 6 0 3 b b 1 6 0 3 b c 1 6 0 3 b d 1 6 0 3 b e 1 6 0 3 b f 1 6 d m a 1 r e q u e s t c a u s e s e l e c t r e g i s t e r ( d m 1 s l ) d m a 0 r e q u e s t c a u s e s e l e c t r e g i s t e r ( d m 0 s l ) u a r t 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( u 0 m r ) u a r t 0 t r a n s m i t b u f f e r r e g i s t e r ( u 0 t b ) u a r t 0 r e c e i v e b u f f e r r e g i s t e r ( u 0 r b ) u a r t 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( u 1 m r ) u a r t 1 t r a n s m i t b u f f e r r e g i s t e r ( u 1 t b ) u a r t 1 r e c e i v e b u f f e r r e g i s t e r ( u 1 r b ) t i m e r a 0 ( t a 0 ) t i m e r a 1 ( t a 1 ) t i m e r a 2 ( t a 2 ) t i m e r b 0 ( t b 0 ) t i m e r b 1 ( t b 1 ) t i m e r b 2 ( t b 2 ) c o u n t s t a r t f l a g ( t a b s r ) o n e - s h o t s t a r t f l a g ( o n s f ) t i m e r a 0 m o d e r e g i s t e r ( t a 0 m r ) t i m e r a 1 m o d e r e g i s t e r ( t a 1 m r ) t i m e r a 2 m o d e r e g i s t e r ( t a 2 m r ) t i m e r b 0 m o d e r e g i s t e r ( t b 0 m r ) t i m e r b 1 m o d e r e g i s t e r ( t b 1 m r ) t i m e r b 2 m o d e r e g i s t e r ( t b 2 m r ) u p - d o w n f l a g ( u d f ) t i m e r a 3 ( t a 3 ) t i m e r a 4 ( t a 4 ) t i m e r a 3 m o d e r e g i s t e r ( t a 3 m r ) t i m e r a 4 m o d e r e g i s t e r ( t a 4 m r ) t r i g g e r s e l e c t r e g i s t e r ( t r g s r ) u a r t 0 b i t r a t e g e n e r a t o r ( u 0 b r g ) u a r t 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( u 0 c 0 ) u a r t 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 ( u 0 c 1 ) u a r t 1 b i t r a t e g e n e r a t o r ( u 1 b r g ) u a r t 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( u 1 c 0 ) u a r t 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 ( u 1 c 1 ) u a r t t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 2 ( u c o n ) c r c d a t a r e g i s t e r ( c r c d ) c r c i n p u t r e g i s t e r ( c r c i n ) c l o c k p r e s c a l e r r e s e t f l a g ( c p s r f ) 7 3 7 4 7 3 7 3 8 3 7 2 8 2 9 1 9 0 9 1 9 2 9 0 9 1 9 0 9 1 9 2 9 0 9 2 5 0 5 0 1 2 7 0 3 e 0 1 6 0 3 e 1 1 6 0 3 e 2 1 6 0 3 e 3 1 6 0 3 e 4 1 6 0 3 e 5 1 6 0 3 e 6 1 6 0 3 e 7 1 6 0 3 e 8 1 6 0 3 e 9 1 6 0 3 e a 1 6 0 3 e b 1 6 0 3 e c 1 6 0 3 e d 1 6 0 3 e e 1 6 0 3 e f 1 6 0 3 f 0 1 6 0 3 f 1 1 6 0 3 f 2 1 6 0 3 f 3 1 6 0 3 f 4 1 6 0 3 f 5 1 6 0 3 f 6 1 6 0 3 f 7 1 6 0 3 f 8 1 6 0 3 f 9 1 6 0 3 f a 1 6 0 3 f b 1 6 0 3 f c 1 6 0 3 f d 1 6 0 3 f e 1 6 0 3 f f 1 6 0 3 c 0 1 6 0 3 c 1 1 6 0 3 c 2 1 6 0 3 c 3 1 6 0 3 c 4 1 6 0 3 c 5 1 6 0 3 c 6 1 6 0 3 c 7 1 6 0 3 c 8 1 6 0 3 c 9 1 6 0 3 c a 1 6 0 3 c b 1 6 0 3 c c 1 6 0 3 c d 1 6 0 3 c e 1 6 0 3 c f 1 6 0 3 d 0 1 6 0 3 d 1 1 6 0 3 d 2 1 6 0 3 d 3 1 6 0 3 d 4 1 6 0 3 d 5 1 6 0 3 d 6 1 6 0 3 d 7 1 6 0 3 d 8 1 6 0 3 d 9 1 6 0 3 d a 1 6 0 3 d b 1 6 0 3 d c 1 6 0 3 d d 1 6 0 3 d e 1 6 0 3 d f 1 6 p o r t p 0 ( p 0 ) p o r t p 1 ( p 1 ) p o r t p 2 ( p 2 ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p d 3 ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p d 4 ) p o r t p 5 ( p 5 ) p o r t p 6 ( p 6 ) p o r t p 7 ( p 7 ) p o r t p 7 d i r e c t i o n r e g i s t e r ( p d 7 ) p o r t p 8 ( p 8 ) p o r t p 8 d i r e c t i o n r e g i s t e r ( p d 8 ) p o r t p 9 ( p 9 ) p o r t p 9 d i r e c t i o n r e g i s t e r ( p d 9 ) p o r t p 1 0 ( p 1 0 ) p o r t p 1 0 d i r e c t i o n r e g i s t e r ( p d 1 0 ) p u l l - u p c o n t r o l r e g i s t e r 0 ( p u r 0 ) p u l l - u p c o n t r o l r e g i s t e r 1 ( p u r 1 ) a - d r e g i s t e r 7 ( a d 7 ) a - d r e g i s t e r 0 ( a d 0 ) a - d r e g i s t e r 1 ( a d 1 ) a - d r e g i s t e r 2 ( a d 2 ) a - d r e g i s t e r 3 ( a d 3 ) a - d r e g i s t e r 4 ( a d 4 ) a - d r e g i s t e r 5 ( a d 5 ) a - d r e g i s t e r 6 ( a d 6 ) a - d c o n t r o l r e g i s t e r 0 ( a d c o n 0 ) a - d c o n t r o l r e g i s t e r 1 ( a d c o n 1 ) d - a r e g i s t e r 0 ( d a 0 ) d - a r e g i s t e r 1 ( d a 1 ) d - a c o n t r o l r e g i s t e r ( d a c o n ) a - d c o n t r o l r e g i s t e r 2 ( a d c o n 2 ) 1 1 8 1 1 8 1 1 7 1 2 6 1 2 6 1 2 6 1 3 2 1 3 2 1 3 2 1 3 2 1 3 3 f l a s h m e m o r y c o n t r o l r e g i s t e r 0 ( f c o n 0 ) ( n o t e ) f l a s h m e m o r y c o n t r o l r e g i s t e r 1 ( f c o n 1 ) ( n o t e ) f l a s h c o m m a n d r e g i s t e r ( f c m d ) ( n o t e ) n o t e : t h i s r e g i s t e r i s o n l y e x i s t i n f l a s h m e m o r y v e r s i o n . 1 5 5 1 3 2 1 3 2
chapter 1 hardware
2 description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ------table of contents------ description the M30218 group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 100-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. they also feature a built-in multiplier and dmac, making them ideal for controlling musical instruments, house- hold appliances and other high-speed processing applications. the M30218 group includes a wide range of products with different internal memory types and sizes and various package types. features ?basic machine instructions ............. compatible with the m16c/60 series ?memory capacity ............................ rom / ram (see figure memory expansion) ?shortest instruction execution time . 100ns (f(x in )=10mhz) ?supply voltage ................................ 4.0v to 5.5v (f(x in )=10mhz) 2.7v to 5.5v (f(x in )=3.5mhz)(note) ?interrupts ........................................ 19 internal and 6 external interrupt sources, 4 software ?multifunction 16-bit timer ................ timer a x 5, timer b x 3 ?fld conrtoller ................................. total 56 pins (high-breakdown-voltage p-channel open-drain output : 52pins) ?serial i/o ......................................... 2 channels for uart or clock synchronous, 1 channels for clock synchronous (max.256 bytes automatic transfer function) ?dmac ............................................. 2 channels (triggers: 15 sources) ?a-d converter ................................. 10 bits x 8 channels ?d-a converter ................................. 8 bits x 2 channels ?crc calculation circuit ................... 1 circuit ?watchdog timer .............................. 1 pin ?programmable i/o .......................... 48 pins ?high-breakdown-voltage output ...... 52 pins ?clock generating circuit .................. 2 built-in clock generation circuit (built-in feedback resistor, and external ceramic or quartz oscillator) note: only mask rom version. applications household appliances, office equipment, audio etc. timer ............................................................. 71 serial i/o ....................................................... 88 a-d converter ............................................. 115 d-a converter ............................................. 125 crc calculation circuit .............................. 127 programmable i/o ports ............................. 129 flash memory ............................................. 154 central processing unit (cpu) ..................... 12 reset............................................................. 15 clock generating circuit ............................... 19 protection ...................................................... 27 interrupts ....................................................... 28 watchdog timer ............................................ 46 dmac ........................................................... 48 fld controller ............................................... 54
3 description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r pin configuration figure 1 shows the pin configuration (top view). pin configuration (top view) figure 1. pin configuration (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 89 9 0 91 92 93 94 95 96 97 98 99 1 00 m 3 0 2 1 8 m c -ax x x f p p 6 0 / f l d 0 p6 1 /fld1 p6 2 /fld2 p6 3 /fld3 p6 4 /fld4 p6 5 /fld5 p6 6 /fld6 p6 7 /fld7 p 5 0 / f l d 8 v c c x i n r e s e t x o u t v s s c n v s s p 8 6 / x c o u t p 8 7 / x c i n p 9 0 / s r d y 2 p 7 6 / t a 3 i n / t a 1 o u t / c l k 1 p 7 7 / t a 4 i n / t a 2 o u t / c t s 1 / r t s 1 / c l k s 1 p 9 4 / s o u t 2 p 9 5 / s c l k 2 1 p 9 6 / d a 1 / s c l k 2 2 p 9 7 / d a 0 / c l k o u t / d i m o u t p 9 2 / s s t b 2 p 9 3 / s i n 2 p 7 3 / t a 0 i n / t a 3 o u t p 7 2 / t b 2 i n p 9 1 / s b u s y 2 package:100p6s-a v ee p10 7 /an7 p10 6 /an6 p10 5 /an5 p10 3 /an3 p10 2 /an2 p10 4 /an4 p10 1 /an1 a v s s p10 0 /an0 v r e f a v c c p 5 1 / f l d 9 p 5 2 / f l d 1 0 p 5 3 / f l d 1 1 p 5 4 / f l d 1 2 p 5 5 / f l d 1 3 p 5 6 / f l d 1 4 p 5 7 / f l d 1 5 p 0 0 / f l d 1 6 p 0 1 / f l d 1 7 p 0 2 / f l d 1 8 p 0 3 / f l d 1 9 p 0 4 / f l d 2 0 p 0 5 / f l d 2 1 p 0 6 / f l d 2 2 v s s p 0 7 / f l d 2 3 v c c p 1 0 / f l d 2 4 p 1 1 / f l d 2 5 p 1 2 / f l d 2 6 p 1 3 / f l d 2 7 p 1 4 / f l d 2 8 p 1 5 / f l d 2 9 p 1 6 / f l d 3 0 p 1 7 / f l d 3 1 p 2 0 / f l d 3 2 p 2 1 / f l d 3 3 p 2 2 / f l d 3 4 p 2 3 / f l d 3 5 p 2 4 / f l d 3 6 p 2 5 / f l d 3 7 p 2 6 / f l d 3 8 p2 7 /fld39 p 3 0 / f l d 4 0 p 3 1 / f l d 4 1 p3 2 /fld42 p3 3 /fld43 p 3 4 / f l d 4 4 p3 5 /fld45 p 3 6 / f l d 4 6 p3 7 /fld47 p4 0 /fld48 p4 1 /fld49 p4 2 /fld50 p4 3 /fld51 p4 4 /t x d0/fld52 p4 5 /r x d0/fld53 p4 6 /clk0/fld54 p47/cts0/rts0/fld55 p 7 5 / t a 2 i n / t a 0 o u t / r x d 1 p 7 4 / t a 1 i n / t a 4 o u t / t x d 1 p 7 1 / t b 1 i n p 7 0 / t b 0 i n p 8 5 / i n t 5 p 8 4 / i n t 4 p 8 3 / i n t 3 p 8 2 / i n t 2 p 8 1 / i n t 1 p 8 0 / i n t 0
4 description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r block diagram figure 2 shows a block diagram of the M30218 group. block diagram of the M30218 group figure 2. block diagram of M30218 group aaaa aaaa timer timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) internal peripheral functions watchdog timer (15 bits) dmac (2 channels) d-a converter (8 bits x 2 channels) a-d converter (10 bits x 8 channels ) si/o2 (clock synchronous ) (256 bytes automatic transfer) system clock generator x in -x out x cin -x cout m16c/60 series16-bit cpu core i/o ports port p0 8 port p1 8 port p2 8 port p3 8 port p4 8 port p5 8 port p6 8 8 r0l r0h r1 h r1l r 2 r 3 a0 a1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb registers isp usp stack pointer vector table intb crc arithmetic circuit (ccitt) (polynomial : x 16 +x 12 +x 5 +1) multiplier 8 8 8 port p10 port p9 port p8 port p7 aaaaaa a aaaa a a aaaa a a aaaa a aaaaaa memory rom (note 1) ram (note 2) (includes fldc,asi/o ram) sb flg pc program counter fluorescent display function (56 contorol pins) (52 high-breakdown-voltage ports) serial i/o uart/clock synchronous si/o (8 bits x 2 channels) note 1: rom size depends on mcu type. note 2: ram size depends on mcu type.
5 description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r rom ram p3, p4, p7 to p10 p0 to p2, p5, p6 ta0, ta1, ta2, ta3, ta4 tb0, tb1, tb2 uart0, uart1 si/o2 table 1. performance outline of M30218 group performance outline table 1 shows a performance outline of M30218 group. item performance number of basic instructions 91 instructions shortest instruction execution time 100ns(f(x in )=10mhz) see figure memory expansion see figure memory expansion 8 bits x 6 8 bit x 5 16 bits x 5 16 bits x 3 (uart or clock synchronous) x 2 (clock synchronous) x 1 (with automatic transfer function) fluorescent display 56 pins a-d converter 10 bits x 8 channels d-a converter 8 bits x 2 dmac 2 channels (triggers :15 sources) crc calculation circuit 1 circuit (polynomial: x 16 + x 12 + x 5 + 1) watchdog timer 15 bits x 1 (with prescaler) interrupt 19 internal and 6 external sources, 4 software sources, 7 levels clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) supply voltage 4.0 to 5.5v (f(x in )=10mhz) 2.7 to 5.5v (f(x in )=3.5mhz) (note) power consumption 18 mw (v cc =3v, f(x in )=5mhz) v cc -48v (output ports : p0 to p2, p5, p6, i/o ports : p3, p4 0 to p4 3 ) 0 to v cc (i/o ports :p4 4 to p4 7 , p7 to p10) - 18ma (p0 to p3, p4 0 to p4 3 , p5, p6) :high-breakdown-voltage, p-channel open-drain - 5ma (p4 4 to p4 7 , p7 to p10) 5ma (p4 4 to p4 7 , p7 to p10) operating ambient temperature C20 to 85 o c device configuration cmos silicon gate package 100-pin plastic mold qfp memory capacity i/o port output port multifunction timer serial i/o i/o withstand voltage output current i/o characteristics h l note: only mask rom version.
6 description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r mitsubishi plans to release the following products in the M30218 group: (1) support for mask rom version and flash memory version (2) memory capacity (3) package 100p6s : plastic molded qfp (mask rom version and flash memory version) figure 4. type no., memory size, and package figure 3. rom expansion r a m s i z e ( b y t e ) 1 2 k 1 k 5 1 2 M30218mc-axxxfp M30218fcfp 1 2 8 k r o m s i z e ( b y t e ) m 3 0 2 1 7 m a - a x x x f p 5 k 9 6 k package type: fp : package 100p6s-a rom no. omitted for flash memory version rom capacity: 2 : 16k bytes 4 : 32k bytes 6 : 48k bytes 8 : 64k bytes a : 96k bytes c : 128k bytes memory type: m : mask rom version f : flash memory version type no. m 3 0 2 1 8 m c ? a x x x f p m16c/21 group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning)
7 pin description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r pin description v c c , v s s c n v s s x i n x o u t a v c c a v s s v e e p 0 0 / f l d 1 6 t o p 0 7 / f l d 2 3 p1 0 /fld 24 to p1 7 /fld 31 p2 0 /fld 32 to p2 7 /fld 39 p3 0 /fld 40 to p3 7 /fld 47 p 4 0 / f l d 4 8 t o p 4 7 / f l d 5 6 s i g n a l n a m e p o w e r s u p p l y i n p u t c n v s s r e s e t i n p u t c l o c k i n p u t c l o c k o u t p u t a n a l o g p o w e r s u p p l y i n p u t p u l l - d o w n p o w e r s o u r c e o u t p u t p o r t p 0 output port p1 output port p2 i/o port p3 i / o p o r t p 4 s u p p l y 2 . 7 v ( n o t e 1 ) t o 5 . 5 v t o t h e v c c p i n . s u p p l y 0 v t o t h e v s s p i n . c o n n e c t a b y p a s s c a p a c i t o r a c r o s s t h e v c c p i n a n d v s s p i n . f u n c t i o n c o n n e c t i t t o t h e v s s p i n . a l o n t h i s i n p u t r e s e t s t h e m i c r o c o m p u t e r . t h e s e p i n s a r e p r o v i d e d f o r t h e m a i n c l o c k g e n e r a t i n g c i r c u i t . c o n n e c t a c e r a m i c r e s o n a t o r o r c r y s t a l b e t w e e n t h e x i n a n d t h e x o u t p i n s . to u s e a n e x t e r n a l l y d e r i v e d c l o c k , i n p u t i t t o t h e x i n p i n a n d l e a v e t h e x o u t p i n o p e n . t h i s p i n i s a p o w e r s u p p l y i n p u t f o r t h e a - d c o n v e r t e r . c o n n e c t t h i s p i n t o v c c . t h i s p i n i s a p o w e r s u p p l y i n p u t f o r t h e a - d c o n v e r t e r . c o n n e c t t h i s p i n t o v s s . t h i s i s a n 8 - b i t c m o s o u t p u t p o r t a n d h i g h - b r e a k d o w n - v o l t a g e p - c h a n n e l o p e n - d r a i n o u t p u t s t r u c t u r e . a p u l l - d o w n r e s i s t o r i s b u i l t i n b e t w e e n p o r t p 0 a n d v e e p i n . a t r e s e t , t h i s p o r t i s s e t t o v e e l e v e l . p 0 f u n c t i o n a s f l d c o n t r o l l e r o u t p u t p i n s a s s e l e c t e d b y s o f t w a r e . this is an 8-bit output port equivalent to p0. pins in this port also function as fld controller output pins as selected by software. this is an 8-bit output port equivalent to p0. a pull-down resistor is not built in between p2 and v ee pin. pins in this port also function as fld controller output pins as selected by software. this is an 8-bit i/o port. a pull-down resistor is not built in between p3 and v ee pin. it has an input/output port direction register that allows the user to set each pin for input or output. this is low-voltage input level, and high-breakdown-voltage p-channel open-drain output structure. pins in this port also function as fld controller output pins as selected by software. t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 3 . t h i s i s l o w - v o l t a g e i n p u t l e v e l . p 4 0 t o p 4 3 i s h i g h - b r e a k d o w n - v o l t a g e p - c h a n n e l o p e n - d r a i n o u t p u t s t r u c t u r e , p 4 4 t o p 4 7 i s c m o s o u t p u t . a p u l l - d o w n r e s i s t o r i s n o t b u i l t i n b e t w e e n p 4 ( p 4 0 t o p 4 3 ) a n d v e e p i n . p i n s i n t h i s p o r t a l s o f u n c t i o n a s f l d c o n t r o l l e r o u t p u t p i n s a s s e l e c t e d b y s o f t w a r e . p 4 4 t o p 4 7 a l s o f u n c t i o n a s u a r t 0 i / o p i n s a s s e l e c t e d b y s o f t w a r e . w h e n s e t f o r i n p u t , t h e u s e r c a n s p e c i f y i n u n i t s o f f o u r b i t s b y s o f t w a r e w h e t h e r o r n o t t h e y a r e t i e d t o a p u l l - u p r e s i s t o r . p i n n a m e input input input output output output output i / o t y p e a n a l o g p o w e r s u p p l y i n p u t input/output input/output r e s e t v r e f t h i s p i n i s a r e f e r e n c e v o l t a g e i n p u t f o r t h e a - d c o n v e r t e r . input r e f e r e n c e v o l t a g e i n p u t a p p l y v o l t a g e s u p p l i e d t o p u l l - d o w n r e s i s t o r s o f p o r t s p 0 t o p 1 , p 5 , p 6 . p5 0 /fld 8 to p5 7 /fld 15 output port p5 this is an 8-bit output port equivalent to p0. pins in this port also function as fld controller output pins as selected by software. output p6 0 /fld 0 to p6 7 /fld 7 output port p6 this is an 8-bit output port equivalent to p0. pins in this port also function as fld controller output pins as selected by software. output
8 pin description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r pin description s i g n a l n a m e function p i n n a m e i/o type i n p u t / o u t p u t input/output i / o p o r t p 9 i/o port p10 p 9 0 t o p 9 7 p10 0 to p10 7 t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 7 . w h e n s e t f o r i n p u t , t h e u s e r c a n s p e c i f y i n u n i t s o f f o u r b i t s b y s o f t w a r e w h e t h e r o r n o t t h e y a r e t i e d t o a p u l l - u p r e s i s t o r . p 9 7 f u n c t i o n a s d - a c o n v e r t e r o u t p u t p i n s , c l o c k o u t p u t p i n s ( s a m e f r e q u e n c y o f x i n / 8 , x i n / 3 2 o r x c i n ) a n d d i m s i g n a l o u t p u t p i n o f f l d c o n t r o l l e r a s s e l e c t e d b y s o f t w a r e . p 9 6 f u n c t i o n a s d - a c o n v e r t e r o u t p u t p i n s a n d c l o c k i / o p i n o f s e r i a l i / o w i t h a u t o m a t i c t r a n s f e r a s s e l e c t e d b y s o f t w a r e . p 9 0 t o p 9 5 f u n c t i o n a s i / o p i n o f s e r i a l i / o w i t h a u t o m a t i c t r a n s f e r a s s e l e c t e d b y s o f t w a r e . t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 7 . w h e n s e t f o r i n p u t , t h e u s e r c a n s p e c i f y i n u n i t s o f f o u r b i t s b y s o f t w a r e w h e t h e r o r n o t t h e y a r e t i e d t o a p u l l - u p r e s i s t o r . p i n s i n t h i s p o r t a l s o f u n c t i o n a s a - d c o n v e r t e r i n p u t p i n s a s s e l e c t e d b y s o f t w a r e . p 7 0 t o p 7 7 i / o p o r t p 7t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 3 . t h i s i s c m o s i n p u t / o u t p u t . w h e n s e t f o r i n p u t , t h e u s e r c a n s p e c i f y i n u n i t s o f f o u r b i t s b y s o f t w a r e w h e t h e r o r n o t t h e y a r e t i e d t o a p u l l - u p r e s i s t o r . p 7 0 t o p 7 2 f u n c t i o n a s t i m e r b 0 t o b 2 i n p u t p i n s a s s e l e c t e d b y s o f t w a r e . p 7 3 f u n c t i o n a s t i m e r a 0 i / o p i n a s s e l e c t e d b y s o f t w a r e . p 7 4 t o p 7 7 f u n c t i o n a s t i m e r a 1 t o a 4 i / o p i n s , a n d u a r t 1 i / o p i n s a s s e l e c t e d b y s o f t w a r e . i n p u t / o u t p u t p 8 0 t o p 8 7 i / o p o r t p 8t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 7 . w h e n s e t f o r i n p u t , t h e u s e r c a n s p e c i f y i n u n i t s o f f o u r b i t s b y s o f t w a r e w h e t h e r o r n o t t h e y a r e t i e d t o a p u l l - u p r e s i s t o r . p 8 0 t o p 8 5 f u n c t i o n a s e x t e r n a l i n t e r r u p t i n p u t p i n s a s s e l e c t e d b y s o f t w a r e . p 8 6 , p 8 7 f u n c t i o n a s s u b - c l o c k i n p u t p i n a s s e l e c t e d b y s o f t w a r e . i n t h i s c a s e , c o n n e c t a q u a r t s o s c i l l a t o r b e t w e e n p 8 6 ( x o u t p i n ) a n d p 8 7 ( x c i n p i n ) i n p u t / o u t p u t n o t e 1 : s u p p l y 4 . 0 v t o 5 . 5 v t o t h e v c c p i n i n f l a s h m e m o r y v e r s i o n .
9 memory m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r operation of functional blocks the M30218 group accommodates certain units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, fld controller, serial i/o, d-a converter, dmac, crc calculation circuit, a-d converter, and i/o ports. the following explains each unit. memory figure 5 is a memory map of the M30218 group. the address space extends the 1m bytes from address 00000 16 to fffff 16 . from fffff 16 down is rom. for example, in the M30218mc-axxxfp, there is 128k bytes of internal rom from e0000 16 to fffff 16 . the vector table for fixed interrupts such as the reset are mapped to fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. from 00400 16 up is ram. for example, in the M30218mc-axxxfp, there is 12k bytes of internal ram from 00400 16 to 033ff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. (from 00400 16 to 004ff 16 is ram for sio2. from 00500 16 to 005df 16 is ram for fld.) the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates the control registers for periph- eral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. figure 5. memory map 0 0 0 0 0 1 6 x x x x x 1 6 f f f f f 1 6 0 0 4 0 0 1 6 0 0 5 0 0 1 6 0 0 5 e 0 1 6 y y y y y 1 6 i nterna l rom area sfr area (for details, see figures 6 and 7) r a m a r e a f o r s i / o 2 f f e 0 0 1 6 f f f d c 1 6 f f f f f 1 6 u n d e f i n e d i n s t r u c t i o n o ver fl o w b r k i n s t r u c t i o n address match s i n g l e s t e p w a t c h d o g t i m e r r e s e t s p e c i a l p a g e v e c t o r t a b l e db c t y p e n o . a d d r e s s x x x x x 1 6 m 3 0 2 1 8 m c m 3 0 2 1 8 f c e0 0 0 0 1 6 a d d r e s s y y y y y 1 6 0 3 3f f 1 6 i n t e r n a l r a m a r e a r a m a r e a f o r f l d ( 2 2 4 b y t e s ) m 3 0 2 1 7 m a e80 0 0 1 6 0 1 7 f f 1 6
10 memory m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 6. location of peripheral unit control registers (1) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 int1 interrupt control register (int1ic) timer b0 interrupt control register (tb0ic) timer b2 interrupt control register (tb2ic) timer a1 interrupt control register (ta1ic) timer a3 interrupt control register (ta3ic) uart0 transmit interrupt control register (s0tic) int2 interrupt control register (int2ic) int0 interrupt control register (int0ic) timer b1 interrupt control register (tb1ic) timer a0 interrupt control register (ta0ic) timer a2 interrupt control register (ta2ic) timer a4 interrupt control register (ta4ic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control register (s1tic) uart1 receive interrupt control register (s1ric) dma1 interrupt control register (dm1ic) dma0 interrupt control register (dm0ic) a-d conversion interrupt control register (adic) dma0 control register (dm0con) dma0 source pointer (sar0) dma0 transfer counter (tcr0) dma0 destination pointer (dar0) dma1 control register (dm1con) dma1 source pointer (sar1) dma1 transfer counter (tcr1) dma1 destination pointer (dar1) watchdog timer start register (wdts) watchdog timer control register (wdc) processor mode register 0 (pm0) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) system clock control register 0 (cm0) system clock control register 1 (cm1) address match interrupt enable register (aier) protect register (prcr) processor mode register 1(pm1) int4 interrupt control register (int4ic) int3 interrupt control register (int3ic) int5 interrupt control register (int5ic) si/o automatic transfer interrupt control register (asioic) fld interrupt control register (fldic) 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 p3 fld/port switch register (p3fpr) p5 digit output set register (p5dor) toff2 time set register (toff2) fld data pointer (flddp) fld output control register (fldcon) p6 digit output set register (p6dor) p4 fld/port switch register (p4fpr) p2 fld/port switch register (p2fpr) tdisp time set register (tdisp) toff1 time set register (toff1) fld mode register (fldm) serial i/o2 automatic transfer data pointer (sio2dp) serial i/o2 control register 1 (sio2con1) serial i/o2 control register 2 (sio2con2) serial i/o2 register / transfer counter (sio2) serial i/o2 control register 3 (sio2con3)
11 memory m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 7. location of peripheral unit control registers (2) 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 dma1 request cause select register (dm1sl) dma0 request cause select register (dm0sl) uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) timer a0 (ta0) timer a1 (ta1) timer a2 (ta2) timer b0 (tb0) timer b1 (tb1) timer b2 (tb2) count start flag (tabsr) one-shot start flag (onsf) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr) up-down flag (udf) timer a3 (ta3) timer a4 (ta4) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) trigger select register (trgsr) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) uart transmit/receive control register 2 (ucon) crc data register (crcd) crc input register (crcin) clock prescaler reset flag (cpsrf) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port p0 (p0) port p1 (p1) port p2 (p2) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) port p5 (p5) port p6 (p6) port p7 (p7) port p7 direction register (pd7) port p8 (p8) port p8 direction register (pd8) port p9 (p9) port p9 direction register (pd9) port p10 (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) a-d register 7 (ad7) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) a-d control register 0 (adcon0) a-d control register 1 (adcon1) d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) a-d control register 2 (adcon2) flash memory control register 0 (fcon0) (note) flash memory control register 1 (fcon1) (note) flash command register (fcmd) (note) note: this re g ister is only exist in flash memory version.
12 cpu m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r central processing unit (cpu) the cpu has a total of 13 registers shown in figure 8. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h, r1h), and low-order bits as (r0l, r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0, r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). figure 8. central processing unit register aaaaaaa aaaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaaa aaaaaaa b15 b0 r3 (note) aaaaaaa b15 b0 a0 (note) aaaaaaa aaaaaaa b15 b0 a1 (note) aaaaaaa aaaaaaa b15 b0 fb (note) aaaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these re g isters consist of two re g ister banks. a a aa aa aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl
13 cpu m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure ca-2 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0. ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged.
14 cpu m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 9. flag register (flg) ?bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details. c a r r y f l a g d e b u g f l a g z e r o f l a g s i g n f l a g r e g i s t e r b a n k s e l e c t f l a g o v e r f l o w f l a g i n t e r r u p t e n a b l e f l a g s t a c k p o i n t e r s e l e c t f l a g r e s e r v e d a r e a p r o c e s s o r i n t e r r u p t p r i o r i t y l e v e l r e s e r v e d a r e a f l a g r e g i s t e r ( f l g ) c d z s b o i u i p l b 0 b 1 5
15 reset m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the h level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 10 shows the example reset circuit. figure 11 shows the reset sequence. figure 10. example reset circuit reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.0v example when f ( x in ) = 10mhz and v cc = 5v . bclk address bclk 24cycles ffffc 16 ffffe 16 content of reset vector x in reset more than 20 cycles are needed (internal clock) (internal address s i g n a l ) figure 11. reset sequence
16 reset m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 12. device's internal status after a reset is cleared x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. (1) (0004 16 ) processor mode register 0 (2) (0005 16 ) processor mode register 1 0 0 (3) (0006 16 ) system clock control register 0 1 00 00 10 0 (4) (0007 16 ) system clock control register 1 0 00 10 00 0 (5) (6) (0009 16 ) address match interrupt enable register 0 0 (7) (12) (13) (21) (22) (23) (20) (8) (0012 16 ) 0 (000f 16 ) watchdog timer control register 0 0? 0???? (0010 16 ) address match interrupt register 0 (0011 16 ) 00 16 00 16 0 0 0 (14) (9) (0014 16 ) address match interrupt register 1 (0015 16 ) (0016 16 ) 0 00 16 00 16 0 0 0 (002c 16 ) dma0 control register 00000?00 (003c 16 ) dma1 control register 00000?00 (0044 16 ) int3 interrupt control register 00?000 (15) (16) (17) (18) (19) (0048 16 ) int4 interrupt control register 00?000 (0049 16 ) int5 interrupt control register 00?000 (29) (30) (31) (32) (33) (34) (35) (36) (37) timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register (38) timer b2 interrupt control register (39) int0 interrupt control register (40) int1 interrupt control register (41) int2 interrupt control register (45) fldc mode register (46) fld output control register serial i/o 2 control register 2 (43) serial i/o 2 control register 3 (44) (42) serial i/o 2 control register 1 (47) tdisp time set register toff1 time set register toff2 time set register p2 fld/port switch register p4 fld/port switch register p6 digit output set register (0055 16 ) (0056 16 ) (0057 16 ) (0058 16 ) (0059 16 ) (005a 16 ) (005b 16 ) (005c 16 ) (005d 16 ) (005e 16 ) (005f 16 ) (0350 16 ) (0351 16 ) (0344 16 ) (0348 16 ) (0342 16 ) (0352 16 ) (0354 16 ) (0356 16 ) (0359 16 ) (035b 16 ) (035d 16 ) (035a 16 ) p3 fld/port switch register a-d conversion interrupt control register si/o automatic transfer interrupt control register fld interrupt control register (004e 16 ) ? 0 0 0 (004f 16 ) (0050 16 ) ? 0 0 0 ? 0 0 0 uart0 transmit interrupt control register uart0 receive interrupt control register (0051 16 ) (0052 16 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 000 00 ? 000 00 ? 000 00 p5 digit output set register (035c 16 ) (000a 16 ) protect register 0 0 0 (10) (11) (004b 16 ) dma0 interrupt control register ? 0 0 0 (004c 16 ) dma1 interrupt control register ? 0 0 0 uart1 transmit interrupt control register uart1 receive interrupt control register (0053 16 ) (0054 16 ) ? 0 0 0 ? 0 0 0 (24) (25) (26) (27) (28) 0 0 0 0 0 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 00 16 00 16 00 16 00 16 00 16
17 reset m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 13. device's internal status after a reset is cleared (0383 16 ) trigger select flag (0384 16 ) up-down flag (52) (51) (0396 16 ) timer a0 mode register (53) (0397 16 ) timer a1 mode register (54) (0398 16 ) timer a2 mode register (57) (039b 16 ) timer b0 mode register (58) (039c 16 ) timer b1 mode register (039d 16 ) timer b2 mode register (70) (55) (0399 16 ) timer a3 mode register (56) (039a 16 ) timer a4 mode register (0382 16 ) one-shot start flag (50) 00 16 00 16 0 00 16 00 16 00 16 00 16 00 16 0? 0000 00? 0000 00? 0000 (03ac 16 ) uart1 transmit/receive control register 0 (75) (03ad 16 ) uart1 transmit/receive control register 1 (76) (03b0 16 ) uart transmit/receive control register 2 (77) (03b8 16 ) dma0 cause select register (78) (03ba 16 ) dma1 cause select register (79) 0 (03a0 16 ) uart0 transmit/receive mode register (71) (03a4 16 ) uart0 transmit/receive control register 0 (72) (03a5 16 ) uart0 transmit/receive control register 1 (73) 00 16 000 1000 000 0010 0 0 (03a8 16 ) uart1 transmit/receive mode register (74) 00 16 000 1000 000 0010 0 0 0 0000 0 00 16 00 16 (03d4 16 ) a-d control register 2 (80) (03d6 16 ) a-d control register 0 (81) (03d7 16 ) a-d control register 1 (82) 0 000 0??? 0 00 16 0 00 0000 count start flag (0380 16 ) 00 16 0 (0381 16 ) clock prescaler reset flag (48) (49) x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. (84) (85) (86) (03e7 16 ) port p3 direction register (87) (03ea 16 ) port p4 direction register (88) (89) (03ef 16 ) port p7 direction register (03f2 16 ) port p8 direction register (03f3 16 ) port p9 direction register (03f6 16 ) port p10 direction register (03fd 16 ) pull-up control register 0 (03fe 16 ) pull-up control register 1 00 16 00 16 00 16 00 16 00 16 00 16 00 16 frame base register (fb) address registers (a0/a1) interrupt table register (intb) user stack pointer (usp) interrupt stack pointer (isp) static base register (sb) flag register (flg) 0000 16 0000 16 00000 16 0000 16 0000 16 0000 16 0000 16 data registers (r0/r1/r2/r3) 0000 16 (03dc 16 ) d-a control register 00 16 (62) (61) (63) (64) (67) (68) (65) (66) (60) (59) (69) (83) 00 16 flash memory control register 0 (note ) flash memory control register 1 (note) flash command register (note) note: this re g ister is onl y exist in flash memor y version. (03b4 16 ) 01 0000 0 (03b5 16 ) 0 (03b6 16 ) 0 00 16 (90) (91) (92) 0
18 software reset m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software reset) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. figure 14 shows the processor mode register 0 and 1. figure 14. processor mode register 0 and 1 processor mode register 0 (note) symbol address when reset pm0 0004 16 xxxx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pm03 reserved bit software reset bit the device is reset when this bit is set to ?? the value of this bit is ??when read. note: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. processor mode register 1 (note) symbol address when reset pm1 0005 16 00xxxxx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 reserved bit must always be set to ? 0 note: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. a a a a a a a a must always be set to 0 0 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. 0 0 0 0 0 reserved bit must always be set to 0 a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
19 clock generating circuit m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. table 2. main clock and sub clock generating circuits main clock generating circuit sub clock generating circuit use of clock ? cpus operating clock source ? cpus operating clock source ? internal peripheral units ? timer a/bs count clock operating clock source source usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator x in , x out x cin , x cout oscillation stop/restart function available available oscillator status immediately after rese t oscillating stopped other externally derived clock can be input example of oscillator circuit figure 15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 16 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 15 and 16 vary with each oscillator used. use the values recom- mended by the manufacturer of your oscillator. microcomputer (built-in feedback resistor) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vcc vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd figure 15. examples of main clock figure 16. examples of sub clock
20 clock generating circuit m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 ?? write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 1 q s r interrupt request level judgment output reset software reset f c cm07=0 cm07=1 f ad aaa aaa divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider x in f 8 f 32 c b b 1/2 c bclk f 8sio2 f 1sio2 clock control figure 17 shows the block diagram of the clock generating circuit. figure 17. clock generating circuit
21 clock generating circuit m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock, after switching the operating clock source of cpu to the sub-clock, reduces the power dissipation. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) sub-clock the sub-clock is generated by the sub-clock oscillation circuit. no sub-clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub-clock can be selected as the bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub-clock oscillation has fully stabilized before switching. after the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. the bclk is derived by dividing the main clock by 8 after a reset. the bclk signal can be output from bclk pin by the bclk output disable bit (bit 7 at address 0004 16 ) in the memory expan- sion and the microprocessor modes. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high- speed/medium-speed to stop mode and at reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) peripheral function clock(f 1 , f 8 , f 32 , f ad , f 1sio2 , f 8sio2 ) the clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. (5) f c32 this clock is derived by dividing the sub-clock by 32. it is used for the timer a and timer b counts. (6) f c this clock has the same frequency as the sub-clock. it is used for the bclk and for the watchdog timer.
22 clock generating circuit m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 18 shows the system clock control registers 0 and 1. system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p9 7 /da 0 0 1 : f c output 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit (valid only in single-chip mode) wait peripheral function clock stop bit 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 3, 4, 5) 0 : on 1 : off main clock division select bit 0 (note 7) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 6) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shiffing to stop mode and at a reset. note 3: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to ?? when main clock oscillation is operating by itself, set system clock select bit (cm07) to ??before setting this bit to ?? note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 5: if this bit is set to ?? x out turns ?? the built-in feedback resistor remains being connected, so x in turns pulled up to x out (?? via the feedback resistor. note 6: set port xc select bit (cm04) to ??and stabilize the sub-clock oscillating before setting to this bit from ??to ? . do not write to both bits at the same time. and also, set the main clock stop bit (cm05) to ??and stabilize the main clock oscillating before setting this bit from ??to ?? note 7: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 8: f c32 is not included. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note4) 0 : clock on 1 : all clocks off (stop mode) note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is ?? if ?? division mode is fixed at 8. note 4: if this bit is set to ?? x out turns ?? and the built-in feedback resistor is cut off. x cin and x cout turn high- impedance state. cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r cm16 cm17 reserved bit always set to ? reserved bit always set to ? main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 0 reserved bit always set to ? reserved bit always set to ? 0 0 a aa a aa a aa a aa a a aa aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a aa figure 18. clock control registers 0 and 1
23 clock output m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r clock output the clock output function select bit (bit 0,1 at address 0006 16 ) allows you to choose the clock from f 8 , f 32 , or f c to be output from the p9 7 /da 0 /clk out /dim out pin. when the wait peripheral function clock stop bit (bit 2 at address 0006 16 ) is set to 1, the output of f 8 and f 32 stop by executing of wait instruction. stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc re- mains above 2v. because the oscillation of bclk, f 1 to f 32 , fc, f c32 , and f ad stops in stop mode, peripheral functions such as the fluorescent display function, serial i/o 2, a-d converter and watchdog timer do not function. however, timer a and timer b operate provided that the event counter mode is set to an external pulse, and uart0 and uart2 functions provided an external clock is selected. table 3 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or an interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. if returning by an interrupt, that interrupt routine is executed. when shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. table 3. port status during stop mode pin states port retains status before stop mode clk out when f c selected h when f 8 , f 32 selected retains status before stop mode wait mode when a wait instruction is executed, bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but bclk and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 4 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or an interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as bclk, the clock that had been selected when the wait instruction was executed. table 4. port status during wait mode pin states port retains status before wait mode clk out when f c selected does not stop when f 8 , f 32 selected does not stop when the wait peripheral function clock stop bit is 0. (note) when the wait peripheral function clock stop bit is 1, the status immediately prior to entering wait mode is maintained. note: attention that reducing the power dissipation is impossible.
24 status transition of bclk m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r cm17 cm16 cm07 cm06 cm05 cm04 operating mode of bclk 0 1 0 0 0 invalid division by 2 mode 1 0 0 0 0 invalid division by 4 mode invalid invalid 0 1 0 invalid division by 8 mode 1 1 0 0 0 invalid division by 16 mode 0 0 0 0 0 invalid no-division mode invalid invalid 1 invalid 0 1 low-speed mode invalid invalid 1 invalid 1 1 low power dissipation mode table 5. operating modes dictated by settings of system clock control registers 0 and 1 status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table wa-4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. when reset, the device starts in division by 8 mode. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high-speed/medium-speed to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. the following shows the operational modes of bclk. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. when reset, the device starts operating from this mode. before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. when going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is divided by 1 to obtain the bclk. (6) low-speed mode f c is used as the bclk. note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub- clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power dissipation mode f c is the bclk and the main clock is stopped. note : before the count source for bclk can be changed from x in to x cin or vice versa, the clock to which the count source is going to be switched must be oscillating stably. allow a wait time in software for the oscillation to stabilize before switching over the clock.
25 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r power control the following is a description of the three available power control modes: modes power control is available in three modes. (a) normal operation mode ? high-speed mode divide-by-1 frequency of the main clock becomes the bclk. the cpu operates with the internal clock selected. each peripheral function operates according to its assigned clock. ? medium-speed mode divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the internal clock selected. each peripheral function oper- ates according to its assigned clock. ? low-speed mode f c becomes the bclk. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. each peripheral function operates according to its assigned clock. ? low power consumption mode the main clock operating in low-speed mode is stopped. the cpu operates according to the f c clock. the fc clock is supplied by the secondary clock. the only peripheral functions that operate are those with the sub-clock selected as the count source. (b) wait mode the cpu operation is stopped. the oscillators do not stop. (c) stop mode all oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in decreasing power consumption. figure 19 shows the state transition diagram of the above modes.
26 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 19. state transition diagram of power control mode transition of stop mode, wait mode transition of normal mode reset medium-speed mode (divided-by-8 mode) interrupt cm10 = ? all oscillators stopped cpu operation stopped medium-speed mode (divided-by-8 mode) bclk : f(x in )/8 cm07 = ?? cm06 = ? low-speed mode high-speed mode main clock is oscillating sub clock is stopped main clock is oscillating sub clock is stopped main clock is stopped sub clock is oscillating main clock is oscillating sub clock is oscillating low power dissipation mode high-speed/medium- speed mode low-speed/low power dissipation mode normal mode stop mode stop mode stop mode all oscillators stopped all oscillators stopped wait mode wait mode wait mode cpu operation stopped cpu operation stopped interrupt wait instruction interrupt wait instruction interrupt wait instruction cm10 = ? interrupt interrupt cm10 = ? bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x in )/8 medium-speed mode (divided-by-8 mode) cm07 = ? cm06 = ? high-speed mode bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x cin ) cm07 = ? bclk : f(x cin ) cm07 = ? main clock is oscillating sub clock is oscillating cm07 = ? (note 1, 3) cm07 = ??(note 1) cm06 = ? cm04 = ? cm07 = ? (note 2) cm07 = ??(note 1) cm06 = ??(note 3) cm04 = ? cm07 = ??(note 2) cm05 = ?? cm05 = ? cm05 = ? cm04 = ? cm04 = ? cm06 = ? (notes 1,3) cm06 = ? cm04 = ? cm04 = ? (notes 1, 3) note 1: switch clock after oscillation of main clock is sufficiently stable. note 2: switch clock after oscillation of sub clock is sufficiently stable. note 3: change cm06 after changing cm17 and cm16. note 4: transit in accordance with arrow. (refer to the following for the transition of normal mode.)
27 protection m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 20 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control reg- ister 0 (address 0006 16 ), and system clock control register 1 (address 0007 16 ) can only be changed when the respective bit in the protect register is set to 1. the system clock control registers 0 and 1 write-enable bit (bit 0 at address 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at address 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. figure 20. protect register p r o t e c t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p r c r0 0 0 a 1 6 x x x x x 0 0 0 2 b i t n a m e b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 0 : w r i t e - i n h i b i t e d 1 : w r i t e - e n a b l e d p r c 1 p r c 0 e n a b l e s w r i t i n g t o p r o c e s s o r m o d e r e g i s t e r s 0 a n d 1 ( a d d r e s s e s 0 0 0 4 1 6 a n d 0 0 0 5 1 6 ) f u n c t i o n 0 : w r i t e - i n h i b i t e d 1 : w r i t e - e n a b l e d e n a b l e s w r i t i n g t o s y s t e m c l o c k c o n t r o l r e g i s t e r s 0 a n d 1 ( a d d r e s s e s 0 0 0 6 1 6 a n d 0 0 0 7 1 6 ) w r n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e .
28 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 21. classification of interrupts interrupt ? ? ? y ? ? ? t software hardware ? y ? t special peripheral i/o (note) ? y ? t undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? y ? ? t reset ________ dbc watchdog timer single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. overview of interrupt type of interrupts figure 21 shows the types of interrupts.
29 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to 1. the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut- ing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o inter- rupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/ o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to 0 and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt re- quest. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
30 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset ____________ reset occurs if an l is input to the reset pin. ________ ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt generated by the watchdog timer. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to 1, a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? dma0 interrupt, dma1 interrupt these are interrupts that dma generates. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0 and uart1 transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0 and uart1 reception interrupt these are interrupts that the serial i/o reception generates. ? si/o automatic transfer interrupt this is an interrupt that the si/o automatic transfer generates. ? timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates ? timer b0 interrupt through timer b2 interrupt these are interrupts that timer b generates. ________ ________ ? int0 interrupt through int5 interrupt ______ ______ an int interrupt occurs if either a rising edge or a falling edge is input to the int pin.
31 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector contains ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use - ffff8 16 to ffffb 16 - reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only. figure 22. format for specifying interrupt vector addresses m i d a d d r e s s l o w a d d r e s s 0 0 0 0h i g h a d d r e s s 0 0 0 0 0 0 0 0 v e c t o r a d d r e s s + 0 v e c t o r a d d r e s s + 1 v e c t o r a d d r e s s + 2 v e c t o r a d d r e s s + 3 l s b m s b interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 22 shows the format for specifying the address. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 6 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. table 6. interrupts assigned to the fixed vector tables and addresses of vector tables
32 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 7. interrupts assigned to the variable vector tables and addresses of vector tables software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked i flag +0 to +3 (note) brk instruction software interrupt number 0 +44 to +47 (note) software interrupt number 11 +48 to +51 (note) software interrupt number 12 +56 to +59 (note) software interrupt number 14 +68 to +71 (note) software interrupt number 17 +72 to +75 (note) software interrupt number 18 +76 to +79 (note) software interrupt number 19 +80 to +83 (note) software interrupt number 20 +84 to +87 (note) software interrupt number 21 +88 to +91 (note) software interrupt number 22 +92 to +95 (note) software interrupt number 23 +96 to +99 (note) software interrupt number 24 +100 to +103 (note) software interrupt number 25 +104 to +107 (note) software interrupt number 26 +108 to +111 (note) software interrupt number 27 +112 to +115 (note) software interrupt number 28 +116 to +119 (note) software interrupt number 29 +120 to +123 (note) software interrupt number 30 +124 to +127 (note) software interrupt number 31 +128 to +131 (note) software interrupt number 32 +252 to +255 (note) software interrupt number 63 to note : address relative to address in interrupt table register (intb). cannot be masked i flag to a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3 timer b0 timer b1 int0 int1 software interrupt +28 to +31 (note) int3 software interrupt number 7 +32 to +35 (note) int4 software interrupt number 8 +36 to +39 (note) int5 software interrupt number 9 dma0 dma1 +60 to +63 (note) software interrupt number 15 si/o automatic transfer +64 to +67 (note) software interrupt number 16 fld timer a4 timer b2 int2 ?variable vector tables the addresses in the variable vector table can be modified, according to the users settings. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the ad- dress the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 7 shows the interrupts assigned to the variable vector tables and addresses of vector tables.
33 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority level selec- tion bit, or processor interrupt priority level (ipl). whether an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 23 shows the memory map of the interrupt control registers.
34 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 23. interrupt control registers symbol address when reset intiic(i=0 to 5) 005d 16 to 005f 16 xx00x000 2 0047 16 to 0049 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 note1 : this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. (note1) interrupt control register(note2) b7 b6 b5 b4 b3 b2 b1 b0 a aa aa a bit name function bit symbol w r symbol address when reset dmiic(i=0, 1) 004b 16 to 004c 16 xxxxx000 2 adic 004e 16 xxxxx000 2 asioic 004f 16 xxxxx000 2 fldic 0050 16 xxxxx000 2 sitic(i=0, 1) 0051 16 , 0053 16 xxxxx000 2 siric(i=0, 1) 0052 16 , 0054 16 xxxxx000 2 taiic(i=0 to 4) 0055 16 to 0059 16 xxxxx000 2 tbiic(i=0 to 2) 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. (note1) note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 a a a a a a a a a a a a a a a a a a a a a a a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
35 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). table 9. interrupt levels enabled according to the contents of the ipl table 8. settings of interrupt priority levels interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table 8 shows the settings of interrupt priority levels and table 9 shows the interrupt levels enabled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another.
36 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
37 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16 . (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (4) saves the content of the temporary register (note) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 24 shows the interrupt response time. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) time from interrupt request is generated to when the instruction then under execution is completed. (b) time in which the instruction sequence is executed. figure 24. interrupt response time
38 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r interrupt sources without priority levels 7 value set in the ipl watchdog timer other not changed 0 variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 11 shows set in the ipl. table 11. relationship between interrupts without interrupt priority levels and ipl stack pointer (sp) value interrupt vector address 16-bit bust 8-bit bus even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) table 10. time required for executing the interrupt sequence reset indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 indeterminate sp-2 sp-4 vec vec+2 pc bclk address bus data bus w r time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction. time (b) is as shown in table 10. ________ note 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. note 2: locate an interrupt vector address in an even address, if possible. figure 25. time required for executing the interrupt sequence
39 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure 26 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m ?1 m ?2 m ?3 m ?4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ?1 m ?2 m ?3 m ?4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m ) figure 26. state of stack before and after acceptance of interrupt request
40 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 27. operation of saving registers (2) stack pointer (sp) contains odd number [sp] (odd) [sp] ?1 (even) [sp] ?2(odd) [sp] ?3 (even) [sp] ?4(odd) [sp] ?5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] ?1(odd) [sp] ?2 (even) [sp] ?3(odd) [sp] ?4 (even) [sp] ?5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h ) the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd- if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 27 shows the operation of the saving registers. note: stack pointer indicated by u flag.
41 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure 28 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. return the other registers saved by software within the interrupt routine using the popm or similar instruc- tion before executing the reit instruction. interrupt resolution circuit when two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. figure 29 shows the circuit that judges the interrupt priority level. figure 28. hardware interrupts priorities ________ reset > dbc > watchdog timer > peripheral i/o > single step > address match
42 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 29. maskable interrupts priorities timer b0 timer a3 int2 timer b1 int3 uart1 reception uart0 reception fld timer a0 uart1 transmission uart0 transmission si/o2 automatic transfer processor interrupt priority level (ipl) interrupt enable flag (i flag) timer b2 int0 watchdog timer reset dbc interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) address match int1 timer a1 int4 timer a4 timer a2 int5 a-d conversion dma1 dma0 interrupt request level judgment output
43 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the inter- rupt enable flag (i flag) and processor interrupt priority level (ipl). the value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. figure 30 shows the address match interrupt-related registers. b i t n a m e b i t s y m b o l s y m b o la d d r e s s w h e n r e s e t a i e r0 0 0 9 1 6 x x x x x x 0 0 2 a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r f u n c t i o n w r a d d r e s s m a t c h i n t e r r u p t 0 e n a b l e b i t 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d a i e r 0 a d d r e s s m a t c h i n t e r r u p t 1 e n a b l e b i t a i e r 1 s y m b o la d d r e s s w h e n r e s e t r m a d 00 0 1 2 1 6 t o 0 0 1 0 1 6 x 0 0 0 0 0 1 6 r m a d 10 0 1 6 1 6 t o 0 0 1 4 1 6 x 0 0 0 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 w r a d d r e s s s e t t i n g r e g i s t e r f o r a d d r e s s m a t c h i n t e r r u p t f u n c t i o nv a l u e s t h a t c a n b e s e t a d d r e s s m a t c h i n t e r r u p t r e g i s t e r i ( i = 0 , 1 ) 0 0 0 0 0 1 6 t o f f f f f 1 6 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d b 0b 7b 0 b 3 ( b 1 9 )( b 1 6 ) b 7b 0 ( b 1 5 )( b 8 ) b 7 ( b 2 3 ) n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . figure 30. address match interrupt-related registers address match interrupt
44 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ______ figure 31. switching condition of int interrupt request set the polarity select bit clear the interrupt request bit to ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to ? (disable interrupt) set the interrupt enable flag to ? (enable interrupt) precautions for interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. (3) external interrupt ________ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 ________ through int 5 regardless of the cpu operation clock. ________ ________ ? when the polarity of the int 0 through int 5 pins is changed, the interrupt request bit is sometimes set to 1. after changing the polarity, set the interrupt request bit to 0. figure 31 shows the procedure for ______ changing the int interrupt generate factor. precautions for interrupts
45 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r precautions for interrupts example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 46 watchdog timer figure 32. block diagram of watchdog timer bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to ?fff 16 1/128 1/16 ?m07 = 0 ?dc7 = 1 ?m07 = 0 ?dc7 = 0 ?m07 = 1 1/2 prescaler watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. when x in is selected for the bclk , bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). thus the watchdog timer's period can be calcu- lated as given below. the watchdog timer's period is, however, subject to an error due to the prescaler. for example, suppose that bclk runs at 10 mhz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 52.4 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 32 shows the block diagram of the watchdog timer. figure 33 shows the watchdog timer-related registers. with x in chosen for bclk watchdog timer period = prescaler dividing ratio (16 or 128) x watchdog timer count (32768) bclk with x cin chosen for bclk watchdog timer period = prescaler dividing ratio (2) x watchdog timer count (32768) bclk
47 watchdog timer m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 33. watchdog timer control and start registers watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 regardless of whatever value is written. reserved bit reserved bit must always be set to ? must always be set to ? 0 0 aa aa a aa aa a a aa aa a a a
48 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 34. block diagram of dmac dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. dmac shares the same data bus with the cpu. the dmac is given a higher right of using the bus than the cpu, which leads to working the cycle stealing method. on this account, the operation from the occurrence of dma transfer request signal to the completion of 1-word (16- bit) or 1-byte (8-bit) data transfer can be performed at high speed. figure 34 shows the block diagram of the dmac. table 12 shows the dmac specifications. figure 35 to figure 36 show the registers used by the dmac. either a write signal to the software dma request bit or an interrupt request signal is used as a dma transfer request signal. but the dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. the dma transfer doesn't affect any interrupts either. if the dmac is active (the dma enable bit is set to 1), data transfer starts every time a dma transfer request signal occurs. if the cycle of the occurrences of dma transfer request signals is higher than the dma transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. for details, see the description of the dma request bit. aa aa aa aa aa aa aa aa aa aa a a aa aa aa aa aa aa aa aa aa aa aa aaaaaa aaaaaa data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) aaaaaaa data bus high-order bits a a a a a a aaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa address bus a a a a dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) aa aa aa aa dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) aa aa (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented b y a dma re q uest. aa aa aa aa aa aa aa a a a a a a a a a a aa aa aa a a a a a a a a
49 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address (note that dma-related registers [0020 16 to 003f 16 ] cannot be accessed) maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) ________ ________ ________ ________ falling edge of int0 or int1 (int0 can be selected by dma0, int1 by dma1) timer a0 to timer a4 interrupt requests timer b0 to timer b2 interrupt requests uart0 transmission and reception interrupt requests uart1 transmission and reception interrupt requests a-d conversion interrupt requests software triggers channel priority dma0 takes precedence if dma0 and dma1 requests are generated simultaneously transfer unit 8 bits or 16 bits transfer address direction forward or fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode ? single transfer mode after the transfer counter underflows, the dma enable bit turns to 0, and the dmac turns inactive ? repeat transfer mode after the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. the dmac remains active unless a 0 is written to the dma enable bit. dma interrupt request generation timing when an underflow occurs in the transfer counter active when the dma enable bit is set to 1, the dmac is active. when the dmac is active, data transfer starts every time a dma transfer request signal occurs. inactive ? when the dma enable bit is set to 0, the dmac is inactive. ? after the transfer counter underflows in single transfer mode at the time of starting data transfer immediately after turning the dmac active, re the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer,and the value of the transfer counter reload register is reloaded to the transfer counter. writing to register registers specified for forward direction transfer are always write enabled. registers specified for fixed address transfer are write-enabled when the dma enable bit is 0. reading the register can be read at any time. however, when the dma enable bit is 1, reading the register set up as the forward register is the same as reading the value of the forward address pointer. table 12. dmac specifications note: dma transfer is not effective to any interrupt. dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. forward address pointer and load timing for transfer counter
50 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 35. dmac-related registers (1) dmai request cause select register symbol address when reset dmisl(i=0,1) 03b8 16 ,03ba 16 00 16 bit name function r bit symbol w b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 dsel1 dsel2 dsel3 software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ?? (when read, the value of this bit is always ?? dsr dmai control register symbol address when reset dmicon(i=0,1) 002c 16 , 003c 16 00000x00 2 bit name function bit symbol r w b7 b6 b5 b4 b3 b2 b1 b0 transfer unit bit select bit 0 : 16 bits 1 : 8 bits dmbit dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit (note 1) 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 3) destination address direction select bit (note 3) 0 : fixed 1 : forward dsd dad note 1: dma request can be cleared by resetting the bit. note 2: this bit can only be set to ?? note 3: source address direction select bit and destination address direction select bit cannot be set to ??simultaneously. b3 b2 b1 b0 0 0 0 0 : falling edge of int0 / int1 pin (note) 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 0 1 1 1 : timer b0 1 0 0 0 : timer b1 1 0 0 1 : timer b2 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart1 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : a-d conversion 1 1 1 1 : inhibited note: address 03b8 16 is for int0; address 03ba 16 is for int1. (note 2) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ??
51 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 36. dmac-related registers (2) b7 b0 b7 b0 (b8) (b15) function rw ?transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw ?source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw ?destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? a a aa aa a aa a aa
52 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 37. example of transfer cycles for a source read (the state of internal bus) bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) 8-bit transfers 16-bit transfers and the source address is even. bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) 16-bit transfers and the source address is odd note: the same timin g chan g es occur with the respective conditions at the destination as at the source. (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. figure 37 shows the example of the transfer cycles (a state of internal bus) for a source read. for conve- nience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle.
53 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (2) dmac transfer any combination of even or odd transfer read and write addresses is possible. table 13 shows the num- ber of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k table 13. no. of dmac transfer cycles singelchip mode transfer unit access address no. of no. of read cycles write cycles 8-bit transfers even 1 1 (dmbit="1") odd 1 1 16-bit transfers even 1 1 (dmbit="0") odd 2 2 internal memory internal rom/ram sfr area 12 coefficient j, k
54 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r fld controller the M30218 group has fluorescent display (fld) drive and control circuits. table 14 shows the fld controller specifications. specification ? 52 pins ( 20 pins can switch general purpose port) ? 4 pins ( 4 pins can switch general purpose port) (a driver must be installed externally) ? used fld output 28 segment x 28 digit (segment number + digit number 56) ? used digit output 40 segment x 16 digit (segment number 40, digit number 16) ? connected to m35501 56 segment x (connect number of m35501) digit (segment number 56, digit number number of m35501 x 16) ? used p4 4 to p4 7 expansion 52 segment x 16 digit (segment number 52, digit number 16) ? 3.2 m s to 819.2 m s (count source x in /32,10mhz) ? 12.8 m s to 3276.8 m s (count source x in /128,10mhz) ? 3.2 m s to 819.2 m s (count source x in /32,10mhz) ? 12.8 m s to 3276.8 m s (count source x in /128,10mhz) ? digit interrupt ? fld blanking interrupt ? key-scan used digit ? key-scan used segment ? digit pulse output function this function automatically outputs digit pulse. ? m35501 connect function the number of digits can be increased easily by using the output of dim out (p9 7 ) as clk for the m35501. ? toff section generate / not generate function this function does not generate toff1 section when the connected outputs are the same. ? gradation display function this function allows each segment to be set for dark or bright display. ? p4 4 to p4 7 expansion function this function provides 16 lines of digit outputs from four ports by attaching a 4 16 decoder. item fld controller port high-breakdown-volt- age output port cmos port display pixel number period dimmer time interrupt key-scan expand function table 14. fld controller specifications
55 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 38. block diagram for fld control circuit 03e8 16 035b 16 8 p4 0 /fld 48 p4 1 /fld 49 p4 2 /fld 50 p4 3 /fld 51 p4 4 /fld 52 p4 5 /fld 53 p4 6 /fld 54 p4 7 /fld 55 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 0500 16 05df 16 03e1 16 8 p1 0 /fld 24 p1 1 /fld 25 p1 2 /fld 26 p1 3 /fld 27 p1 4 /fld 28 p1 5 /fld 29 p1 6 /fld 30 p1 7 /fld 31 main address bus local address bus fld automatic display ram p6 0 /fld 0 p6 1 /fld 1 p6 2 /fld 2 p6 3 /fld 3 p6 4 /fld 4 p6 5 /fld 5 p6 6 /fld 6 p6 7 /fld 7 035d 16 8 03e9 16 8 p5 0 /fld 8 p5 1 /fld 9 p5 2 /fld 10 p5 3 /fld 11 p5 4 /fld 12 p5 5 /fld 13 p5 6 /fld 14 p5 7 /fld 15 main data bus local data bus fld blanking interrupt fld digit interrupt fldc mode register (0350 16 ) fld data pointer reload register (0358 16 ) fld data pointer (0358 16 ) timing generator address decoder 03e4 16 0359 16 8 p2 0 /fld 32 p2 1 /fld 33 p2 2 /fld 34 p2 3 /fld 35 p2 4 /fld 36 p2 5 /fld 37 p2 6 /fld 38 p2 7 /fld 39 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 03e5 16 035a 16 8 p3 0 /fld 40 p3 1 /fld 41 p3 2 /fld 42 p3 3 /fld 43 p3 4 /fld 44 p3 5 /fld 45 p3 6 /fld 46 p3 7 /fld 47 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 03e0 16 8 p0 0 /fld 16 p0 1 /fld 17 p0 2 /fld 18 p0 3 /fld 19 p0 4 /fld 20 p0 5 /fld 21 p0 6 /fld 22 p0 7 /fld 23 dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld 035c 16 03ec 16 fld/port switch register digit output set register
56 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 39. fldc-related register(1) fldc mode register symbol address when reset fldm 0350 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 automatic display control bit 0 : general-purpose mode 1 : automatic display mode fldm0 fldm1 fldm2 fldm3 display start bit 0 : stop display 1 : display (start to display by switching ??to ?? tscan control bits 00 : fld digit interrupt (at rising edge of each digit) 01 : 1 x tdisp 10 : 2 x tdisp 11 : 3 x tdisp 0 : 16 timing mode 1 : 32 timing mode timing number control bit gradation display mode selection control bit 0 : not selecting 1 : selecting (note ) fldm4 fldm5 note : when a gradation display mode is selected, a number of timing is max. 16 timing. (set the timing number control bit to ??) tdisp counter count source selection bit 0 : f(x in )/32 1 : f(x in )/128 fldm6 high-breakdown voltage port drivability select bit 0 : drivability strong 1 : drivability weak fldm7 fld output control register symbol address when reset fldcon 0351 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 fldcon7 fldcon5 fldcon4 fldcon2 fldcon0 fldcon6 p4 4 to p4 7 fld output reverse bit p4 4 to p4 7 fld toff is invalid bit 0 : perform normally 1 : toff is invalid p9 7 dimmer output control bit 0 : output normally 1 : dimmer output cmos ports: section of toff generate/not generate bit 0 : section of toff does not generate 1 : section of toff generates high-breakdown-voltage ports: section of toff generate/not generate bit 0 : section of toff does not generate 1 : section of toff generates toff2 set/reset change bit 0 : gradation display data is reset at toff2 (set at toff1) 1 : gradation display data is set at toff2 (reset at toff1) w r a aa a aa a aa a aa a aa a aa 0 : output normally 1 : reverse output nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be 0. nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be 0. tdisp time set register symbol address when reset tdisp 0352 16 00 16 values that can be set b7 b0 counts tdisp time. count source is selected by tdisp counter count source select bit. w r a a aa aa 0 16 to ff 16 function fld blanking interrupt (at falling edge of last digit) } b3b2 w r a aa a a aa aa a aa a aa a a aa aa a a aa aa a aa aa a a aa aa
57 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 40. fldc-related register(2) toff1 time set register symbol address when reset toff1 0354 16 ff 16 w r b7 b0 function values that can be set counts toff1 time. count source is selected by tdisp counter count source select bit. 3 to ff 16 toff2 time set register symbol address when reset toff2 0356 16 ff 16 w r b7 b0 counts toff2 time. count source is selected by tdisp counter count source select bit. 3 to ff 16 fld data pointer symbol address when reset flddp 0358 16 indeterminate w r b7 b0 counts fld output timing. set this register to ?ld output data - 1 ? 1 to 1f 16 note: reading the fld data pointer takes out the count at that moment. 0 : normal port 1 : fld output port port p2 fld / port switch register symbol address when reset p2fpr 0359 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p2fpr0 p2fpr2 p2fpr1 p2fpr3 p2fpr4 p2fpr6 p2fpr5 p2fpr7 port p2 0 fld/port switch bit 0 : normal port 1 : fld output port port p2 1 fld/port switch bit 0 : normal port 1 : fld output port port p2 2 fld/port switch bit 0 : normal port 1 : fld output port port p2 3 fld/port switch bit 0 : normal port 1 : fld output port port p2 4 fld/port switch bit 0 : normal port 1 : fld output port port p2 5 fld/port switch bit 0 : normal port 1 : fld output port port p2 6 fld/port switch bit 0 : normal port 1 : fld output port port p2 7 fld/port switch bit function values that can be set function values that can be set bit name function bit symbol a a aa aa a aa a aa a aa a aa a aa a aa a a aa aa a a aa aa a aa a aa
58 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 41. fldc-related register(3) 0 : normal port 1 : fld output port port p3 fld / port switch register symbol address when reset p3fpr 035a 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p3fpr0 p3fpr2 p3fpr1 p3fpr3 p3fpr4 p3fpr6 p3fpr5 p3fpr7 port p3 0 fld/port switch bit 0 : normal port 1 : fld output port port p3 1 fld/port switch bit 0 : normal port 1 : fld output port port p3 2 fld/port switch bit 0 : normal port 1 : fld output port port p3 3 fld/port switch bit 0 : normal port 1 : fld output port port p3 4 fld/port switch bit 0 : normal port 1 : fld output port port p3 5 fld/port switch bit 0 : normal port 1 : fld output port port p3 6 fld/port switch bit 0 : normal port 1 : fld output port port p3 7 fld/port switch bit bit name function bit symbol a a a a a a a a a a a a a a a a a a a a 0 : normal port 1 : fld output port port p4 fld / port switch register symbol address when reset p4fpr 035b 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p4fpr0 p4fpr2 p4fpr1 p4fpr3 p4fpr4 p4fpr6 p4fpr5 p4fpr7 port p4 0 fld/port switch bit 0 : normal port 1 : fld output port port p4 1 fld/port switch bit 0 : normal port 1 : fld output port port p4 2 fld/port switch bit 0 : normal port 1 : fld output port port p4 3 fld/port switch bit 0 : normal port 1 : fld output port port p4 4 fld/port switch bit 0 : normal port 1 : fld output port port p4 5 fld/port switch bit 0 : normal port 1 : fld output port port p4 6 fld/port switch bit 0 : normal port 1 : fld output port port p4 7 fld/port switch bit bit name function bit symbol a a a a a a a a a a a a a a a a a a a a 0 : fld output 1 : digit output port p5 digit output set register symbol address when reset p5dor 035c 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p5dor0 p5dor2 p5dor1 p5dor3 p5dor4 p5dor6 p5dor5 p5dor7 port p5 0 fld/digit switch bit 0 : fld output 1 : digit output port p5 1 fld/digit switch bit 0 : fld output 1 : digit output port p5 2 fld/digit switch bit 0 : fld output 1 : digit output port p5 3 fld/digit switch bit 0 : fld output 1 : digit output port p5 4 fld/digit switch bit 0 : fld output 1 : digit output port p5 5 fld/digit switch bit 0 : fld output 1 : digit output port p5 6 fld/digit switch bit 0 : fld output 1 : digit output port p5 7 fld/digit switch bit bit name function bit symbol a a a a a a a a a a a a a a a a a a a a a a
59 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 42. fldc-related register(4) 0 : fld output 1 : digit output port p6 digit output set register symbol address when reset p6dor 035d 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p6dor0 p6dor2 p6dor1 p6dor3 p6dor4 p6dor6 p6dor5 p6dor7 port p6 0 fld/digit switch bit 0 : fld output 1 : digit output port p6 1 fld/digit switch bit 0 : fld output 1 : digit output port p6 2 fld/digit switch bit 0 : fld output 1 : digit output port p6 3 fld/digit switch bit 0 : fld output 1 : digit output port p6 4 fld/digit switch bit 0 : fld output 1 : digit output port p6 5 fld/digit switch bit 0 : fld output 1 : digit output port p6 6 fld/digit switch bit 0 : fld output 1 : digit output port p6 7 fld/digit switch bit bit name function bit symbol a a a a a a a a a a a a a a a a a a a a a a
60 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 43. segment/digit setting example fld automatic display pins p0 to p6 are the pins capable of automatic display output for the fld. the fld start operating by setting the automatic display control bit (bit 0 at address 0350 16 ) to 1. there is the fld output function that outputs ram contents from the port every timing or the digit output function that drives the port high with digit timing. the fld can be displayed using the fld output for the segments and the digit or fld output for the digits. when using the fld output for the digits, be sure to write digit display patterns to the ram in advance. the remaining segment and digit lines can be used as general-purpose ports. settings of each port are shown below. table 15. pins in fld automatic display mode port name automatic display pins setting method p5, p6 fld 0 to fld 15 p0, p1 fld 16 to fld 31 p2, p3, fld 32 to fld 51 p4 4 to p4 3 p4 4 to p4 7 fld 52 to fld 55 the individual bits of the digit output set register (address 035c 16 , 035d 16 ) can set each pin either fld port (0) or digit port (1). when the pins are set for the digit port, the digit pulse output func- tion is enabled, so the digit pulses can always be output regardless the value of fld automatic display ram. fld exclusive use port (automatic display control bit (bit 0 of ad- dress 0350 16 )=1) the individual bits of the fld/port switch register (addresses 0359 16 to 035b 16 ) can set each pin to either fld port (1) or gen- eral-purpose port (0). the individual bits of the fld/port switch register (address 035b 16 ) can set each pin to either fld port (1) or general-purpose port (0). the digit pulse output function turns to available, and the digit pulse can output by setting of the fld output set register (address 0351 16 ). the port output format is the cmos output. when using the port as a display pin, a driver must be installed externally. port p5 port p0 number of segments number of digits port p6 36 16 port p1 setting example 1 shown below is a register setup example where only fld output is used. in this case, the digit display output pattern must be set in the fld automatic display ram in advance. 1 1 1 1 1 1 1 1 fld 32 (seg output) fld 33 (seg output) fld 34 (seg output) fld 35 (seg output) fld 36 (seg output) fld 37 (seg output) fld 38 (seg output) fld 39 (seg output) fld 16 (seg output) fld 17 (seg output) fld 18 (seg output) fld 19 (seg output) fld 20 (seg output) fld 21 (seg output) fld 22 (seg output) fld 23 (seg output) fld 0 (dig output ) fld 1 (dig output) fld 2 (dig output) fld 3 (dig output) fld 4 (dig output) fld 5 (dig output) fld 6 (dig output) fld 7 (dig output) 0 0 0 0 0 0 0 0 fld 8 (dig output) fld 9 (dig output) fld 10 (dig output) fld 11 (dig output) fld 12 (dig output) fld 13 (dig output) fld 14 (dig output) fld 15 (dig output) 0 0 0 0 0 0 0 0 fld 24 (seg output) fld 25 (seg output) fld 26 (seg output) fld 27 (seg output) fld 28 (seg output) fld 29 (seg output) fld 30 (seg output) fld 31 (seg output) port p2 1 1 1 1 1 1 1 1 fld 40 (seg output) fld 41 (seg output) fld 42 (seg output) fld 43 (seg output) fld 44 (seg output) fld 45 (seg output) fld 46 (seg output) fld 47 (seg output) port p3 1 1 1 1 0 0 0 0 fld 48 (seg output) fld 49 (seg output) fld 50 (seg output) fld 51 (seg output) fld 52 (port output) fld 53 (port output) fld 54 (port output) fld 55 (port output) port p4 port p5 port p0 port p6 28 12 port p1 setting example 2 shown below is a register setup example where both fld output and digit waveform output are used. in this case, because the digit display output is automatically generated, there is no need to set the display pattern in the fld automatic display ram. 1 1 1 1 1 1 1 1 fld 32 (seg output) fld 33 (seg output) fld 34 (seg output) fld 35 (seg output) fld 36 (seg output) fld 37 (seg output) fld 38 (seg output) fld 39 (seg output) fld 16 (seg output) fld 17 (seg output) fld 18 (seg output) fld 19 (seg output) fld 20 (seg output) fld 21 (seg output) fld 22 (seg output) fld 23 (seg output) fld 0 (dig output) fld 1 (dig output) fld 2 (dig output) fld 3 (dig output) fld 4 (dig output) fld 5 (dig output) fld 6 (dig output) fld 7 (dig output) 1 1 1 1 1 1 1 1 fld 8 (dig output) fld 9 (dig output) fld 10 (dig output) fld 11 (dig output) fld 12 (seg output) fld 13 (seg output) fld 14 (seg output) fld 15 (seg output) 1 1 1 1 0 0 0 0 fld 24 (seg output) fld 25 (seg output) fld 26 (seg output) fld 27 (seg output) fld 28 (seg output) fld 29 (seg output) fld 30 (seg output) fld 31 (seg output) port p2 1 1 1 1 0 0 0 0 fld 40 (seg output) fld 41 (seg output) fld 42 (seg output) fld 43 (seg output) fld 44 (port output) fld 45 (port output) fld 46 (port output) fld 47 (port output) port p3 0 0 0 0 0 0 0 0 fld 48 (port output) fld 49 (port output) fld 50 (port output) fld 51 (port output) fld 52 (port output) fld 53 (port output) fld 54 (port output) fld 55 (port output) port p4 dig output : this output is connected to digit of the fld. seg output : this output is connected to segment of the fld. port output : this output is g eneral-purpose port ( used pro g ram). dig output : this output is connected to digit of the fld. seg output : this output is connected to segment of the fld. port output : this output is general-purpose port ( used program). the contents of digit output set register (035c 16 , 035d 16 ) fld/port switch register (0359 16 , 035b 16 ) number of segments number of digits the contents of digit output set register (035c 16 , 035d 16 ) fld/port switch register (0359 16 , 035b 16 )
61 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r fld automatic display ram the fld automatic display ram uses the 224 bytes of addresses 0500 16 to 05df 16 . for fld, the 3 modes of 16-timing ordinary mode, 16-timing?gradation display mode and 32-timing mode are available depending on the number of timings and the use/not use of gradation display. the automatic display ram in each mode is as follows: (1) 16-timing?ordinary mode this mode is used when the display timing is 16 or less. the 112 bytes of addresses 0570 16 to 05df 16 are used as a fld display data store area. because addresses 0500 16 to 056f 16 are not used as the automatic display ram, they can be the ordinary ram. (2) 16-timing?gradation display mode this mode is used when the display timing is 16 or less, in which mode each segment can be set for dark or bright display. the 224 bytes of addresses 0500 16 to 05df 16 are used. the 112 bytes of addresses 0570 16 to 05df 16 are used as an fld display data store area, while the 112 bytes of addresses 0500 16 to 056f 16 are used as a gradation display control data store area. (3) 32-timing mode this mode is used when the display timing is 16 or greater. this mode can be used for up to 32-timing. the 224 bytes of addresses 0500 16 to 05df 16 are used as an fld display data store area. the fld data pointer (address 0358 16 ) is a register to count display timings. this pointer has a reload register and when the terminal count is reached, it starts counting over again after being reloaded with the initial count. make sure the timing count C 1 is set to the fld data pointer. when writing data to this address, the data is written to the fld data pointer reload register; when reading data from this address, the value in the fld data pointer is read. figure 44. fld automatic display ram assignment 16-timing?rdinary mode 05df 16 0570 16 0500 16 05df 16 0500 16 05df 16 0570 16 0500 16 16-timing?radation display mode 32-timing mode 1 to 32 timing display data stored area gradation display control data stored area 1 to 16 timing display data stored area 1 to 16 timing display data stored area not used
62 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r data setup (1) 16-timing?ordinary mode the area of addresses 0570 16 to 05df 16 are used as a fld automatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p4 is stored at address 0570 16 , the last data of fld port p3 is stored at address 0580 16 , the last data of fld port p2 is stored at address 0590 16 , the last data of fld port p1 is stored at address 05a0 16 , the last data of fld port p0 is stored at address 05b0 16 , the last data of fld port p5 is stored at address 05c0 16 , and the last data of fld port p6 is stored at address 05d0 16 , to assign in sequence from the last data respectively. the first data of the fld port p4, p3, p2, p1, p0, p5, and p6 is stored at an address which adds the value of (the timing number C 1) to the corresponding address 0570 16 , 0580 16 , 0590 16 , 05a0 16 , 05b0 16 , 05c0 16 and 05df 16 . set the fld data pointer reload register to the value given by the number of digits C 1. (2) 16-timing?gradation display mode display data setting is performed in the same way as that of the 16-timing?ordinary mode. gradation display control data is arranged at an address resulting from subtracting 0070 16 from the display data store address of each timing and pin. bright display is performed by setting 0, and dark display is performed by setting 1 . (3) 32-timing mode the area of addresses 0500 16 to 05df 16 are used as a fld automatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p4 is stored at address 0500 16 , the last data of fld port p3 is stored at address 0520 16 , the last data of fld port p2 is stored at address 0540 16 , the last data of fld port p1 is stored at address 0560 16 , the last data of fld port p0 is stored at address 0580 16 , the last data of fld port p5 is stored at address 05a0 16 , and the last data of fld port p6 is stored at address 05c0 16 , to assign in sequence from the last data respectively . the first data of the fld port p4, p3, p2, p0, p1, p5, and p6 is stored at an address which adds the value of (the timing number C 1) to the corresponding address 0500 16 , 0520 16 , 0540 16 , 0560 16 , 0580 16 , 05a0 16 and 05c0 16 . set the fld data pointer reload register to the value given by the number of digits - 1. figure 45. example of using the fld automatic display ram in 16-timing?ordinary mode number of timing: 8 (fld data pointer reload register = 7) address 058f 16 0571 16 0572 16 0573 16 0574 16 0575 16 0576 16 0577 16 0578 16 0579 16 057a 16 057b 16 057c 16 057d 16 057e 16 057f 16 0580 16 0581 16 0582 16 0583 16 0584 16 0585 16 0586 16 0587 16 0588 16 0589 16 058a 16 058b 16 058c 16 058d 16 058e 16 0590 16 0591 16 0592 16 0593 16 0594 16 0595 16 0596 16 0597 16 0598 16 0599 16 059a 16 059b 16 059c 16 059d 16 059e 16 059f 16 05a1 16 05a2 16 05a3 16 05a4 16 05a5 16 05a6 16 05a7 16 05a8 16 05a9 16 05aa 16 05ab 16 05ac 16 05ad 16 05ae 16 05af 16 05a0 16 0570 16 the last timing (the last data of fldp4) timing for start (the first data of fldp4) the last timing (the last data of fldp3) timing for start (the first data of fldp3) the last timing (the last data of fldp2) timing for start (the first data of fldp2) the last timing (the last data of fldp1) timing for start (the first data of fldp1) 76543210 bit address 05b1 16 05b2 16 05b3 16 05b4 16 05b5 16 05b6 16 05b7 16 05b8 16 05b9 16 05ba 16 05bb 16 05bc 16 05bd 16 05be 16 05bf 16 05b0 16 the last timing (the last data of fldp0) fldp0 data area timing for start (the first data of fldp0) 76543210 bit 05c1 16 05c2 16 05c3 16 05c4 16 05c5 16 05c6 16 05c7 16 05c8 16 05c9 16 05ca 16 05cb 16 05cc 16 05cd 16 05ce 16 05cf 16 05c0 16 05d1 16 05d2 16 05d3 16 05d4 16 05d5 16 05d6 16 05d7 16 05d8 16 05d9 16 05da 16 05db 16 05dc 16 05dd 16 05de 16 05df 16 05d0 16 the last timing (the last data of fldp5) fldp5 data area timing for start (the first data of fldp5) the last timing (the last data of fldp6) fldp6 data area timing for start (the first data of fldp6) fldp1 data area fldp2 data area fldp4 data area fldp3 data area
63 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 46. example of using the fld automatic display ram in 16-timing?radation display mode number of timing: 15 (fld data pointer reload register = 14) address 058f 16 0571 16 0572 16 0573 16 0574 16 0575 16 0576 16 0577 16 0578 16 0579 16 057a 16 057b 16 057c 16 057d 16 057e 16 057f 16 0580 16 0581 16 0582 16 0583 16 0584 16 0585 16 0586 16 0587 16 0588 16 0589 16 058a 16 058b 16 058c 16 058d 16 058e 16 0590 16 0591 16 0592 16 0593 16 0594 16 0595 16 0596 16 0597 16 0598 16 0599 16 059a 16 059b 16 059c 16 059d 16 059e 16 059f 16 05a1 16 05a2 16 05a3 16 05a4 16 05a5 16 05a6 16 05a7 16 05a8 16 05a9 16 05aa 16 05ab 16 05ac 16 05ad 16 05ae 16 05af 16 05a0 16 05b1 16 05b2 16 05b3 16 05b4 16 05b5 16 05b6 16 05b7 16 05b8 16 05b9 16 05ba 16 05bb 16 05bc 16 05bd 16 05be 16 05bf 16 05b0 16 0570 16 the last timing (the last data of fldp4) 76543210 bit the last timing (the last data of fldp3) the last timing (the last data of fldp2) the last timing (the last data of fldp1) the last timing (the last data of fldp0) fldp4 data area fldp3 data area fldp2 data area fldp1 data area fldp0 data area 05c1 16 05c2 16 05c3 16 05c4 16 05c5 16 05c6 16 05c7 16 05c8 16 05c9 16 05ca 16 05cb 16 05cc 16 05cd 16 05ce 16 05cf 16 05c0 16 the last timing (the last data of fldp5) fldp5 data area 05d1 16 05d2 16 05d3 16 05d4 16 05d5 16 05d6 16 05d7 16 05d8 16 05d9 16 05da 16 05db 16 05dc 16 05dd 16 05de 16 05df 16 05d0 16 the last timing (the last data of fldp6) fldp6 data area address 051f 16 0501 16 0502 16 0503 16 0504 16 0505 16 0506 16 0507 16 0508 16 0509 16 050a 16 050b 16 050c 16 050d 16 050e 16 050f 16 0510 16 0511 16 0512 16 0513 16 0514 16 0515 16 0516 16 0517 16 0518 16 0519 16 051a 16 051b 16 051c 16 051d 16 051e 16 0520 16 0521 16 0522 16 0523 16 0524 16 0525 16 0526 16 0527 16 0528 16 0529 16 052a 16 052b 16 052c 16 052d 16 052e 16 052f 16 0531 16 0532 16 0533 16 0534 16 0535 16 0536 16 0537 16 0538 16 0539 16 053a 16 053b 16 053c 16 053d 16 053e 16 053f 16 0530 16 0541 16 0542 16 0543 16 0544 16 0545 16 0546 16 0547 16 0548 16 0549 16 054a 16 054b 16 054c 16 054d 16 054e 16 054f 16 0540 16 0500 16 the last timing (the last data of fldp4) 76543210 bit the last timing (the last data of fldp3) the last timing (the last data of fldp2) the last timing (the last data of fldp1) the last timing (the last data of fldp0) fldp4 gradation display data area fldp3 gradation display data area fldp2 gradation display data area fldp1 gradation display data area fldp0 gradation display data area 0551 16 0552 16 0553 16 0554 16 0555 16 0556 16 0557 16 0558 16 0559 16 055a 16 055b 16 055c 16 055d 16 055e 16 055f 16 0550 16 the last timing (the last data of fldp5) fldp5 gradation display data area 0561 16 0562 16 0563 16 0564 16 0565 16 0566 16 0567 16 0568 16 0569 16 056a 16 056b 16 056c 16 056d 16 056e 16 056f 16 0560 16 the last timing (the last data of fldp6) fldp6 gradation display data area timing for start (the first data of fldp4) timing for start (the first data of fldp3) timing for start (the first data of fldp2) timing for start (the first data of fldp1) timing for start (the first data of fldp0) timing for start (the first data of fldp5) timing for start (the first data of fldp6) timing for start (the first data of fldp4) timing for start (the first data of fldp3) timing for start (the first data of fldp2) timing for start (the first data of fldp1) timing for start (the first data of fldp0) timing for start (the first data of fldp5) timing for start (the first data of fldp6)
64 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 47. example of using the fld automatic display ram in 32-timing mode number of timing: 20 (fld data pointer reload register = 19) address 058f 16 0571 16 0572 16 0573 16 0574 16 0575 16 0576 16 0577 16 0578 16 0579 16 057a 16 057b 16 057c 16 057d 16 057e 16 057f 16 0580 16 0581 16 0582 16 0583 16 0584 16 0585 16 0586 16 0587 16 0588 16 0589 16 058a 16 058b 16 058c 16 058d 16 058e 16 0590 16 0591 16 0592 16 0593 16 0594 16 0595 16 0596 16 0597 16 0598 16 0599 16 059a 16 059b 16 059c 16 059d 16 059e 16 059f 16 05a1 16 05a2 16 05a3 16 05a4 16 05a5 16 05a6 16 05a7 16 05a8 16 05a9 16 05aa 16 05ab 16 05ac 16 05ad 16 05ae 16 05af 16 05a0 16 05b1 16 05b2 16 05b3 16 05b4 16 05b5 16 05b6 16 05b7 16 05b8 16 05b9 16 05ba 16 05bb 16 05bc 16 05bd 16 05be 16 05bf 16 05b0 16 0570 16 76543210 bit fldp0 data area 05c1 16 05c2 16 05c3 16 05c4 16 05c5 16 05c6 16 05c7 16 05c8 16 05c9 16 05ca 16 05cb 16 05cc 16 05cd 16 05ce 16 05cf 16 05c0 16 the last timing (the last data of fldp5) fldp5 data area 05d1 16 05d2 16 05d3 16 05d4 16 05d5 16 05d6 16 05d7 16 05d8 16 05d9 16 05da 16 05db 16 05dc 16 05dd 16 05de 16 05df 16 05d0 16 the last timing (the last data of fldp6) fldp6 data area address 051f 16 0501 16 0502 16 0503 16 0504 16 0505 16 0506 16 0507 16 0508 16 0509 16 050a 16 050b 16 050c 16 050d 16 050e 16 050f 16 0510 16 0511 16 0512 16 0513 16 0514 16 0515 16 0516 16 0517 16 0518 16 0519 16 051a 16 051b 16 051c 16 051d 16 051e 16 0520 16 0521 16 0522 16 0523 16 0524 16 0525 16 0526 16 0527 16 0528 16 0529 16 052a 16 052b 16 052c 16 052d 16 052e 16 052f 16 0531 16 0532 16 0533 16 0534 16 0535 16 0536 16 0537 16 0538 16 0539 16 053a 16 053b 16 053c 16 053d 16 053e 16 053f 16 0530 16 0541 16 0542 16 0543 16 0544 16 0545 16 0546 16 0547 16 0548 16 0549 16 054a 16 054b 16 054c 16 054d 16 054e 16 054f 16 0540 16 0500 16 the last timing (the last data of fldp4) 76543210 bit the last timing (the last data of fldp3) the last timing (the last data of fldp2) the last timing (the last data of fldp1) the last timing (the last data of fldp0) fldp4 data area fldp3 data area fldp2 data area fldp1 data area 0551 16 0552 16 0553 16 0554 16 0555 16 0556 16 0557 16 0558 16 0559 16 055a 16 055b 16 055c 16 055d 16 055e 16 055f 16 0550 16 0561 16 0562 16 0563 16 0564 16 0565 16 0566 16 0567 16 0568 16 0569 16 056a 16 056b 16 056c 16 056d 16 056e 16 056f 16 0560 16 timing for start (the first data of fldp0) timing for start (the first data of fldp5) timing for start (the first data of fldp6) timing for start (the first data of fldp4) timing for start (the first data of fldp3) timing for start (the first data of fldp2) timing for start (the first data of fldp1)
65 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 48. fldc timing toff1 tdisp toff1 toff2 tdisp ?rayscale display mode is not selected (address 0350 16 bit 5 = ?? ?rayscale display mode is selected and set for bright display (address 0350 16 bit 5 = ??and the corresponding grayscale display control data = ?? low output period for blurring prevention display output period display output period low output period for blurring prevention ?rayscale display mode is selected and set for dark display (address 0350 16 bit 5 = ??and the corresponding grayscale display control data = ?? low output period for dark display timing setting each timing is set by the fldc mode register, tdisp time set register, toff1 time set register, and toff2 time set register. ?tdisp time setting the tdisp time represents the length of display timing. in non-gradation display mode, it consists of a fld display output period and a toff1 time. in gradation display mode, it consists of the display output period and toff1 time plus a low signal output period for dark display. set the tdisp time by the tdisp counter count source select bit of the fldc mode register and the tdisp time set register. supposing that the value of the tdisp time set register is n, the tdisp time is represented as tdisp = (n+1) x t (t: count source). when the tdisp counter count source select bit of the fldc mode register is 0 and the value of the tdisp time set register is 200 (c8 16 ), the tdisp time is: tdisp = (200+1) x 3.2 (at x in = 10 mhz) = 643 m s. when reading the tdisp time set register, the value in the counter is read out. ?toff1 time setting the toff1 time represents a non-output (low signal output) time to prevent blurring of fld, and to dim the display. use the toff1 time set register to set this toff1 time. make sure the value set to toff1 is smaller than tdisp and toff2. supposing that the value of the toff1 time set register is n1, the toff1 time is represented as toff1 = n1 x t. when the tdisp counter count source select bit of the fldc mode register is 0 and the value of the toff1 time set register is 30 (1e 16 ), toff1 = 30 x 3.2 (at x in = 10 mhz) = 96 m s. ?toff2 time setting the toff2 time is provided for dark display. for bright display, the fld display output remains effective until the counter that is counting tdisp reaches the terminal count. for dark display, however, l (or off) signal is output when the counter that is counting toff2 reaches the terminal count. this toff2 time setting is valid only for fld ports which are in the gradation display mode and whose gradation display control ram value is 1 . set the toff2 time by the toff2 time set register. make sure the value set to toff2 is smaller than tdisp but larger than toff1. supposing that the value of the toff2 time set register is n2, the toff2 time is repre- sented as toff2 = n2 x t. when the tdisp counter count source select bit of the fldc mode register is 0 and the value of the toff2 time set register is 180 (b4 16 ), toff2 = 180 x 3.2 (at x in = 10 mhz) = 576 m s.
66 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 49. timing using digit interrupt fld digit output tdisp repeat synchronous tn tn-1 tn-2 t4 t3 t2 t1 tn tn-1 tn-2 t4 toff1 fld digit interrupt generated at the rising edge of digit ( each timing) fld automatic display start automatic display starts by setting both the automatic display control bit (bit 0 of address 0350 16 ) and the display start bit (bit 1 of address 0350 16 ) to 1. the ram content at a location apart from the start address of the automatic display ram for each port by (fld data pointer (address 0358 16 ) C 1) is output to each port. the fld data pointer (address 0358 16 ) counts down in the tdisp interval. when the count ff 16 is reached, the pointer is reloaded and starts counting over again. before setting the display start bit (bit 1 of address 0350 16 ) to 1, be sure to set the fld/port switch register, fld/dig switch register, fldc mode register, tdisp time set register, toff1 time set register, toff2 time set register, and fld data pointer. during fld automatic display, bit 1 of the fldc mode register (address 0350 16 ) always keeps 1, and fld automatic display can be interrupted by writing 0 to bit 1. key-scan and interrupt either a fld digit interrupt or fld blanking interrupt can be selected using the tscan control bits (bits 2, 3 of address 0350 16 ). the fld digit interrupt is generated when the toff1 time in each timing expires (at rising edge of digit output). key scanning that makes use of fld digits can be achieved using each fld digit interrupt. to use fld digit interrupts for key scanning, follow the procedure described below. (1) read the port value each time the interrupt occurs. (2) the key is fixed on the last digit interrupt. the digit positions output can be determined by reading the fld data pointer (address 0358 16 ).
67 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 50. timing using fld blanking interrupt tdisp tscan tn tn-1 tn-2 t4 t3 t2 t1 tn tn-1 tn-2 segment setting by software fld blanking interrupt generated at the falling of edge of the last digit fld digit output repeat synchronous the fld blanking interrupt is generated when the fld data pointer (address 0358 16 ) reaches ff 16 . the fld automatic display output is turned off for a duration of 1 x tdisp, 2 x tdisp, or 3 x tdisp depending on post-interrupt settings. during this time, key scanning that makes use of fld segments can be achieved. when a key-scan is performed with the segment during key-scan blanking period tscan, take the following sequence: 1. write 0 to bit 0 of the fldc mode register (address 0350 16 ). 2. set the port corresponding to the segment for key-scan to the output port. 3. perform the key-scan. 4. after the key-scan is performed, write 1 to bit 0 of fldc mode register (address 0350 16 ). ?note: when performing a key-scan according to the above steps 1 to 4, take the following points into consideration. 1. do not set 0 in bit 1 of the fldc mode register (address 0350 16 ). 2. do not set 1 in the ports corresponding to digits.
68 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r p4 4 to p4 7 expansion function p4 4 to p4 7 are cmos output-type ports. fld digit outputs can be increased as many as 16 lines by con- necting a 4-bit to 16-bit decoder to these ports. p4 4 to p4 7 have the function to allow for connection to a 4- bit to 16-bit decoder. (1) p4 4 to p4 7 toff invalid function this function disables the toff1 time and toff2 time and outputs display data for the duration of tdisp. (see figure 51.) this can be accomplished by setting the p4 4 to p4 7 toff disable bit (address 0350 16 bit 2) to 1. unlike the toff section generate/not generate function, this function disables all display data. (2) dimmer signal output function this function allows a dimmer signal creation signal to be output from dim out (p9 7 ). the dimmer function can be materialized by controlling the decoder with this signal. (see figure 51.) this function can be set by writing p9 7 dimmer output control bit (bit 4 of address 0351 16 ) to 1. (3) p4 4 to p4 7 fld output reverse bit p4 4 to p4 7 are provided with a function to reverse the polarity of the fld output. this function is useful in adjusting the polarity when using an externally installed driver. the output polarity can be reversed by setting bit 0 of the fld output control register (address 0351 16 ) to 1 . figure 51. p 4 to p4 7 fld output pulses tdisp toff2 toff1 for dimmer signal dimout(p9 7 ) fld output ?rayscale display mode is not selected ?rayscale display mode is selected and set for bright display (grayscale display control data = ?? ?rayscale display mode is selected and set for dark display (grayscale display control data = ?? ?rayscale display mode is selected and toff2 set/reset bit is ?? (grayscale display control data = ?? output selecting p4 4 to p4 7 toff invalid
69 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r toff2 set/reset change bit in gradation display mode, the values set by the toff2 time set register (toff2) are effective. when the fld output control register (bit 7 of address 0351 16 ) in the initial state = 0, ram data is output to the fld output ports (set) at the time that is set by toff1 and is turned to 0 (reset) at the time that is set by toff2. when bit 7 = 1, ram data is output (set) at the time that is set by toff2 and is turned to 0 (reset) when the tdisp time expires. toff section generate/not generate function the function is for reduction of useless noises which generated as every switching of ports, because of the combined capacity of among fld ports. in case the continuous data output to each fld ports, the toff1 section of the continuous parts is not generated. (see figure 52) if it needs toff1 section on fld pulses, set cmos ports: section of toff generate / not generate bit to 1 and set high-breakdown-voltage ports: section of toff generate / not generate bit to 1 . high-breakdown- voltage ports (p5, p6, p3, p2, p1, p0, p4 0 to p4 3 , total 52 pins) generate toff1 section, by setting high- breakdown-voltage ports: section of toff generate / not generate bit to 1 . the cmos ports ( p4 4 to p4 7 , total 4 pins ) generate toff1 section, by setting high-breakdown-voltage ports: section of toff generate / not generate bit to 1. figure 52. toff section generated/not generated function p1x p2x p1x p2x ??output output waveform when ?igh- breakdown-voltage ports: section of toff generate/not generate bit?bit 6 of 0351 16 ) is ?? tdisp toff1 section of toff1 is not generated because of output is same. output waveform when ?igh- breakdown-voltage ports: section of toff generate/not generate bit?bit 6 of 0351 1 6 ) is ?? ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output section of toff1 is not generated because of output is same.
70 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 53. digit pulses output function digit pulses output function p5 0 to p5 7 and p6 0 to p6 7 allow digit pulses to be output using the fld/digit switch register. set the digit output set register by writing as many consecutive 1s as the timing count from p6 0 . the contents of fld automatic display ram for the ports that have been selected for digit output are disabled, and the pulse shown in figure 53 is output automatically. in gradation display mode use, t off2 time becomes effective for the port which selected digit output. because the contents of fld automatic display ram are disabled, the segment data can be changed easily even when segment data and digit data coexist at the same address in the fld automatic display ram. this function is effective in 16-timing normal mode and 16-timing gradation display mode. if a value is set exceeding the timing count (fld data pointer reload register's set value + 1) for any port, the output of such port is l. low-order 4bits of the data pointer fedcba 0 1 2 3 4 5 6 7 8 9 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 tdisp toff1
71 timer m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r timer there are eight 16-bit timers. these timers can be classified by function into timers a (five) and timers b (three). all these timers function independently. figure 54 shows the block diagram of timers. figure 54. timer block diagram ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ta0 in / ta3 out ta1 in / ta4 out ta2 in / ta0 out ta3 in / ta1 out ta4 in / ta2 out tb0 in tb1 in tb2 in timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 f 1 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt timer b0 interrupt timer b1 interrupt timer b2 interrupt noise filter noise filter noise filter noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? reset clock prescaler
72 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r timer a figure 55 shows the block diagram of timer a. figures 56 to 58 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer's over flow. ? one-shot timer mode: the timer stops counting when the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. figure 55. block diagram of timer a figure 56. timer a-related registers (1) c o u n t e r ( 1 6 ) c o u n t s t a r t f l a g ( a d d r e s s 0 3 8 0 1 6 ) u p c o u n t / d o w n c o u n t t a ia d d r e s s e st a jt a kt a i o u t t i m e r a 00 3 8 7 1 6 0 3 8 6 1 6 t i m e r a 4t i m e r a 1t i m e r a 3 t i m e r a 10 3 8 9 1 6 0 3 8 8 1 6 t i m e r a 0t i m e r a 2t i m e r a 4 t i m e r a 20 3 8 b 1 6 0 3 8 a 1 6 t i m e r a 1t i m e r a 3t i m e r a 0 t i m e r a 30 3 8 d 1 6 0 3 8 c 1 6 t i m e r a 2t i m e r a 4t i m e r a 1 t i m e r a 4 0 3 8 f 1 6 0 3 8 e 1 6 t i m e r a 3t i m e r a 0t i m e r a 2 a l w a y s d o w n c o u n t e x c e p t i n e v e n t c o u n t e r m o d e r e l o a d r e g i s t e r ( 1 6 ) l o w - o r d e r 8 b i t s h i g h - o r d e r 8 b i t s c l o c k s o u r c e s e l e c t i o n t i m e r ( g a t e f u n c t i o n ) t i m e r o n e s h o t p w m f 1 f 8 f 3 2 e x t e r n a l t r i g g e r t a i i n ( i = 0 t o 4 ) t b 2 o v e r f l o w e v e n t c o u n t e r f c 3 2 c l o c k s e l e c t i o n t a j o v e r f l o w ( j = i - 1 . n o t e , h o w e v e r , t h a t j = 4 w h e n i = 0 ) p u l s e o u t p u t t o g g l e f l i p - f l o p t a i o u t ( i = 0 t o 4 ) d a t a b u s l o w - o r d e r b i t s d a t a b u s h i g h - o r d e r b i t s u p / d o w n f l a g d o w n c o u n t ( a d d r e s s 0 3 8 4 1 6 ) t a k o v e r f l o w ( k = i + 1 . n o t e , h o w e v e r , t h a t k = 0 w h e n i = 4 ) p o l a r i t y s e l e c t i o n timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b 1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit a a a a a a a a a a a a a a a a a a a a a a a a
73 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 57. timer a-related registers (2) t i m e r a 4 u p / d o w n f l a g t i m e r a 3 u p / d o w n f l a g t i m e r a 2 u p / d o w n f l a g t i m e r a 1 u p / d o w n f l a g t i m e r a 0 u p / d o w n f l a g t i m e r a 2 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t t i m e r a 3 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t t i m e r a 4 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t s y m b o la d d r e s sw h e n r e s e t u d f0 3 8 4 1 6 0 0 1 6 t a 4 p t a 3 p t a 2 p u p / d o w n f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 t a 4 u d t a 3 u d t a 2 u d t a 1 u d t a 0 u d 0 : d o w n c o u n t 1 : u p c o u n t t h i s s p e c i f i c a t i o n b e c o m e s v a l i d w h e n t h e u p / d o w n f l a g c o n t e n t i s s e l e c t e d f o r u p / d o w n s w i t c h i n g c a u s e 0 : t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g d i s a b l e d 1 : t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g e n a b l e d w h e n n o t u s i n g t h e t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g f u n c t i o n , s e t t h e s e l e c t b i t t o 0 s y m b o la d d r e s sw h e n r e s e t t a b s r0 3 8 0 1 6 0 0 1 6 c o u n t s t a r t f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 t i m e r b 2 c o u n t s t a r t f l a g t i m e r b 1 c o u n t s t a r t f l a g t i m e r b 0 c o u n t s t a r t f l a g t i m e r a 4 c o u n t s t a r t f l a g t i m e r a 3 c o u n t s t a r t f l a g t i m e r a 2 c o u n t s t a r t f l a g t i m e r a 1 c o u n t s t a r t f l a g t i m e r a 0 c o u n t s t a r t f l a g 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g t b 2 s t b 1 s t b 0 s t a 4 s t a 3 s t a 2 s t a 1 s t a 0 s s y m b o la d d r e s sw h e n r e s e t t a 00 3 8 7 1 6 , 0 3 8 6 1 6 i n d e t e r m i n a t e t a 10 3 8 9 1 6 , 0 3 8 8 1 6 i n d e t e r m i n a t e t a 20 3 8 b 1 6 , 0 3 8 a 1 6 i n d e t e r m i n a t e t a 30 3 8 d 1 6 , 0 3 8 c 1 6 i n d e t e r m i n a t e t a 40 3 8 f 1 6 , 0 3 8 e 1 6 i n d e t e r m i n a t e b 7b 0b 7b 0 ( b 1 5 ) ( b 8 ) t i m e r a i r e g i s t e r ( n o t e ) w r t i m e r m o d e0 0 0 0 1 6 t o f f f f c o u n t s a n i n t e r n a l c o u n t s o u r c e f u n c t i o n v a l u e s t h a t c a n b e s e t e v e n t c o u n t e r m o d e c o u n t s p u l s e s f r o m a n e x t e r n a l s o u r c e o r t i m e r o v e r f l o w0 0 0 0 1 6 t o f f f f 1 6 o n e - s h o t t i m e r m o d e0 0 0 0 1 6 t o f f f f 1 6 c o u n t s a o n e s h o t w i d t h p u l s e w i d t h m o d u l a t i o n m o d e ( 1 6 - b i t p w m ) f u n c t i o n s a s a 1 6 - b i t p u l s e w i d t h m o d u l a t o r 0 0 1 6 t o f e 1 6 ( b o t h h i g h - o r d e r a n d l o w - o r d e r a d d r e s s e s ) 0 0 0 0 1 6 t o f f f e 1 6 n o t e : r e a d a n d w r i t e d a t a i s i n 1 6 - b i t u n i t s . p u l s e w i d t h m o d u l a t i o n m o d e ( 8 - b i t p w m ) t i m e r l o w - o r d e r a d d r e s s f u n c t i o n s a s a n 8 - b i t p r e s c a l e r a n d h i g h - o r d e r a d d r e s s f u n c t i o n s a s a n 8 - b i t p u l s e w i d t h m o d u l a t o r
74 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 58 timer a-related registers (3) s y m b o la d d r e s sw h e n r e s e t c p s r f0 3 8 1 1 6 0 x x x x x x x 2 c l o c k p r e s c a l e r r e s e t f l a g b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 c l o c k p r e s c a l e r r e s e t f l a g 0 : n o e f f e c t 1 : p r e s c a l e r i s r e s e t ( w h e n r e a d , t h e v a l u e i s 0 ) c p s r w r n o t h i n g i s a s s i g n e d . t h e s e b i t s c a n n e i t h e r b e s e t n o r r e s e t . w h e n r e a d , t h e i r c o n t e n t s a r e i n d e t e r m i n a t e . t a 1 t g l s y m b o la d d r e s sw h e n r e s e t t r g s r0 3 8 3 1 6 0 0 1 6 t i m e r a 1 e v e n t / t r i g g e r s e l e c t b i t 0 0 : i n p u t o n t a 1 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 0 o v e r f l o w i s s e l e c t e d 1 1 : t a 2 o v e r f l o w i s s e l e c t e d t r i g g e r s e l e c t r e g i s t e r b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : i n p u t o n t a 2 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 1 o v e r f l o w i s s e l e c t e d 1 1 : t a 3 o v e r f l o w i s s e l e c t e d 0 0 : i n p u t o n t a 3 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 2 o v e r f l o w i s s e l e c t e d 1 1 : t a 4 o v e r f l o w i s s e l e c t e d 0 0 : i n p u t o n t a 4 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 3 o v e r f l o w i s s e l e c t e d 1 1 : t a 0 o v e r f l o w i s s e l e c t e d t i m e r a 2 e v e n t / t r i g g e r s e l e c t b i t t i m e r a 3 e v e n t / t r i g g e r s e l e c t b i t t i m e r a 4 e v e n t / t r i g g e r s e l e c t b i t w r t a 1 t g h t a 2 t g l t a 2 t g h t a 3 t g l t a 3 t g h t a 4 t g l t a 4 t g h b 1 b 0 b 3 b 2 b 5 b 4 b 7 b 6 n o t e : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . w h e n t a i i n i s s e l e c t e d , t a i o u t a s s i g n e d o n s a m e p i n c a n n o t b e u s e d . ( i = 0 t o 4 ) t a 1 o s t a 2 o s t a 0 o s o n e - s h o t s t a r t f l a g s y m b o la d d r e s sw h e n r e s e t o n s f0 3 8 2 1 6 0 0 x 0 0 0 0 0 2 t i m e r a 0 o n e - s h o t s t a r t f l a g t i m e r a 1 o n e - s h o t s t a r t f l a g t i m e r a 2 o n e - s h o t s t a r t f l a g t i m e r a 3 o n e - s h o t s t a r t f l a g t i m e r a 4 o n e - s h o t s t a r t f l a g t a 3 o s t a 4 o s b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 n o t h i n g i s a s s i g n e d . t h i s b i t c a n n e i t h e r b e s e t n o r r e s e t . w h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e . t a 0 t g l t a 0 t g h 0 0 : i n p u t o n t a 0 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 4 o v e r f l o w i s s e l e c t e d 1 1 : t a 1 o v e r f l o w i s s e l e c t e d t i m e r a 0 e v e n t / t r i g g e r s e l e c t b i t b 7 b 6 n o t e : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . w h e n t a i i n i s s e l e c t e d , t a i o u t a s s i g n e d o n s a m e p i n c a n n o t b e u s e d . ( i = 0 t o 4 ) w r 1 : t i m e r s t a r t w h e n r e a d , t h e v a l u e i s 0
75 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing countin g divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows tai in pin function programmable i/o port or gate input tai out pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the tai in pins input signal ? pulse output function each time the timer underflows, the tai out pins polarity is reversed (1) timer mode in this mode, the timer counts an internally generated count source. (see table16.) figure 59 shows the timer ai mode register in timer mode. table 16. specifications of timer mode n o t e 1 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . n o t e 2 : t h e b i t c a n b e 0 o r 1 . n o t e 3 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . t i m e r a i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 t o 4 )0 3 9 6 1 6 t o 0 3 9 a 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 0 : t i m e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a i o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 1 ) ( t a i o u t p i n i s a p u l s e o u t p u t p i n ) g a t e f u n c t i o n s e l e c t b i t 0 x ( n o t e 2 ) : g a t e f u n c t i o n n o t a v a i l a b l e ( t a i i n p i n i s a n o r m a l p o r t p i n ) 1 0 : t i m e r c o u n t s o n l y w h e n t a i i n p i n i s h e l d l ( n o t e 3 ) 1 1 : t i m e r c o u n t s o n l y w h e n t a i i n p i n i s h e l d h ( n o t e 3 ) b 4 b 3 m r 2 m r 1 m r 3 0 ( m u s t a l w a y s b e f i x e d t o 0 i n t i m e r m o d e ) 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 b 7 b 6 t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t 00 0 figure 59. timer ai mode register in timer mode
76 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. timers a0 and a1 can count a single-phase external signal. timers a2, a3, and a4 can count a single-phase and a two-phase external signal. table 17 lists timer specifications when counting a single-phase external signal. figure 60 shows the timer ai mode register in event counter mode. table 18 lists timer specifications when counting a two-phase external signal. figure 61 shows the timer ai mode register in event counter mode. table 17. timer specifications in event counter mode (when not processing two-phase pulse signal) item specification count source ?external signals input to tai in pin (effective edge can be selected by software) ?tb2 overflow, taj overflow count operation ?up count or down count can be selected by external signal or software ? when the timer overflows or underflows, the reload register's content is reloaded and the timer starts over again. (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows tai in pin function programmable i/o port or count source input tai out pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register write to timer ?when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ?when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ?free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ?pulse output function each time the timer overflows or underflows, the tai out pins polarity is reversed note: this does not apply when the free-run function is selected. b i t n a m ef u n c t i o n t i m e r a i m o d e r e g i s t e r n o t e 1 : i n e v e n t c o u n t e r m o d e , t h e c o u n t s o u r c e i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) . n o t e 2 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . n o t e 3 : v a l i d o n l y w h e n c o u n t i n g a n e x t e r n a l s i g n a l . n o t e 4 : w h e n a n l s i g n a l i s i n p u t t o t h e t a i o u t p i n , t h e d o w n c o u n t i s a c t i v a t e d . w h e n h , t h e u p c o u n t i s a c t i v a t e d . s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 , 1 )0 3 9 6 1 6 , 0 3 9 7 1 6 0 0 1 6 w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e ( n o t e 1 ) b 1 b 0 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a i o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 2 ) ( t a i o u t p i n i s a p u l s e o u t p u t p i n ) c o u n t p o l a r i t y s e l e c t b i t ( n o t e 3 ) m r 2 m r 1 m r 3 0 ( m u s t a l w a y s b e f i x e d t o 0 i n e v e n t c o u n t e r m o d e ) t c k 0 c o u n t o p e r a t i o n t y p e s e l e c t b i t 01 0 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e 1 : c o u n t s e x t e r n a l s i g n a l ' s r i s i n g e d g e u p / d o w n s w i t c h i n g c a u s e s e l e c t b i t 0 : u p / d o w n f l a g ' s c o n t e n t 1 : t a i o u t p i n ' s i n p u t s i g n a l ( n o t e 4 ) 0 : r e l o a d t y p e 1 : f r e e - r u n t y p e b i t s y m b o l t c k 1 i n v a l i d i n e v e n t c o u n t e r m o d e c a n b e 0 o r 1 t m o d 1 figure 60. timer ai mode register in event counter mode
77 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item specification count source ?two-phase pulse signals input to tai in or tai out pin count operation ?up count or down count can be selected by two-phase pulse signal ?when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read out by reading timer a2, a3, or a4 register write to timer ?when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter ?when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.) select function ?normal processing operation the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h ?multiply-by-4 processing operation if the phase relationship is such that the tai in pin goes h when the input signal on the tai out pin is h, the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the tai in pin goes l when the input signal on the tai out pin is h, the timer counts down rising and falling edges on the tai out and tai in pins. note: this does not apply when the free-run function is selected. table 18. timer specifications in event counter mode (when processing two-phase pulse signal with timer a2,a3 and a4 tai out up count up count up count down count down count down count tai in (i=2,3) tai out tai in (i=3,4) count up all edges count up all ed g es count down all edges count down all ed g es
78 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r b i t s y m b o lb i t n a m ef u n c t i o n b i t n a m ef u n c t i o n n o t e 1 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d n o t e 2 : t h i s b i t i s v a l i d w h e n o n l y c o u n t i n g a n e x t e r n a l s i g n a l . n o t e 3 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . n o t e 4 : t h i s b i t i s v a l i d f o r t i m e r a 3 m o d e r e g i s t e r . f o r t i m e r a 2 a n d a 4 m o d e r e g i s t e r s , t h i s b i t c a n b e 0 o r 1 . n o t e 5 : w h e n p e r f o r m i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g , m a k e s u r e t h e t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g o p e r a t i o n s e l e c t b i t ( a d d r e s s 0 3 8 4 1 6 ) i s s e t t o 1 . a l s o , a l w a y s b e s u r e t o s e t t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) t o 0 0 . t i m e r a i m o d e r e g i s t e r ( w h e n n o t u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 2 t o 4 )0 3 9 8 1 6 t o 0 3 9 a 1 6 0 0 1 6 b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a i o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 1 ) ( t a i o u t p i n i s a p u l s e o u t p u t p i n ) c o u n t p o l a r i t y s e l e c t b i t ( n o t e 2 ) m r 2 m r 1 m r 3 0 ( m u s t a l w a y s b e 0 i n e v e n t c o u n t e r m o d e ) t c k 1 t c k 0 01 0 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e s 1 : c o u n t s e x t e r n a l s i g n a l ' s r i s i n g e d g e s u p / d o w n s w i t c h i n g c a u s e s e l e c t b i t 0 : u p / d o w n f l a g ' s c o n t e n t 1 : t a i o u t p i n ' s i n p u t s i g n a l ( n o t e 3 ) w r c o u n t o p e r a t i o n t y p e s e l e c t b i t t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g o p e r a t i o n s e l e c t b i t ( n o t e 4 ) ( n o t e 5 ) 0 : r e l o a d t y p e 1 : f r e e - r u n t y p e 0 : n o r m a l p r o c e s s i n g o p e r a t i o n 1 : m u l t i p l y - b y - 4 p r o c e s s i n g o p e r a t i o n n o t e 1 : t h i s b i t i s v a l i d f o r t i m e r a 3 m o d e r e g i s t e r . f o r t i m e r a 2 a n d a 4 m o d e r e g i s t e r s , t h i s b i t c a n b e 0 o r 1 . n o t e 2 : w h e n p e r f o r m i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g , m a k e s u r e t h e t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g o p e r a t i o n s e l e c t b i t ( a d d r e s s 0 3 8 4 1 6 ) i s s e t t o 1 . a l s o , a l w a y s b e s u r e t o s e t t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) t o 0 0 . t i m e r a i m o d e r e g i s t e r ( w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 2 t o 4 )0 3 9 8 1 6 t o 0 3 9 a 1 6 0 0 1 6 b 7b 6 b 5b 4b 3 b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 0 ( m u s t a l w a y s b e 0 w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) 0 ( m u s t a l w a y s b e 0 w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) m r 2 m r 1 m r 3 0 ( m u s t a l w a y s b e 0 w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) t c k 1 t c k 0 01 0 1 ( m u s t a l w a y s b e 1 w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) w r c o u n t o p e r a t i o n t y p e s e l e c t b i t t w o - p h a s e p u l s e p r o c e s s i n g o p e r a t i o n s e l e c t b i t ( n o t e 1 ) ( n o t e 2 ) 0 : r e l o a d t y p e 1 : f r e e - r u n t y p e 0 : n o r m a l p r o c e s s i n g o p e r a t i o n 1 : m u l t i p l y - b y - 4 p r o c e s s i n g o p e r a t i o n 0 0 1 figure 61. timer ai mode register in event counter m
79 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item specification count source f1, f 8 , f 32 , f c32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 tai in pin function programmable i/o port or trigger input tai out pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ?when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) (3) one-shot timer mode in this mode, the timer operates only once. (see table 19.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 62 shows the timer ai mode register in one-shot timer mode. table 19. timer specifications in one-shot timer mode figure 62. timer ai mode register in one-shot timer mode b i t n a m ef u n c t i o n b i t s y m b o l t i m e r a i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 t o 4 )0 3 9 6 1 6 t o 0 3 9 a 1 6 0 0 1 6 b 7b 6b 5 b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 1 0 : o n e - s h o t t i m e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a i o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 1 ) ( t a i o u t p i n i s a p u l s e o u t p u t p i n ) m r 2 m r 1 w r m r 3 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 b 7 b 6 t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t 10 0 0 : o n e - s h o t s t a r t f l a g i s v a l i d 1 : s e l e c t e d b y e v e n t / t r i g g e r s e l e c t r e g i s t e r t r i g g e r s e l e c t b i t e x t e r n a l t r i g g e r s e l e c t b i t ( n o t e 2 ) 0 : f a l l i n g e d g e o f t a i i n p i n ' s i n p u t s i g n a l ( n o t e 3 ) 1 : r i s i n g e d g e o f t a i i n p i n ' s i n p u t s i g n a l ( n o t e 3 ) n o t e 1 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d n o t e 2 : v a l i d o n l y w h e n t h e t a i i n p i n i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) . i f t i m e r o v e r f l o w i s s e l e c t e d , t h i s b i t c a n b e 1 o r 0 . n o t e 3 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . 0 ( m u s t a l w a y s b e 0 i n o n e - s h o t t i m e r m o d e )
80 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 20.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 63 shows the timer ai mode register in pulse width modulation mode. figure 64 shows the example of how a 16-bit pulse width modulator operates. figure 65 shows the example of how an 8-bit pulse width modulator operates. table 20. timer specifications in pulse width modulation mode figure 63. timer ai mode register in pulse width modulation mode item specification count source f 1 , f 8 , f 32 , f c32 count operation ? the timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ?the timer is not affected by a trigger that occurs when counting 16-bit pwm ?high level width n / fi n : set value ?cycle time (2 16 -1) / fi fixed 8-bit pwm ?high level width n x (m+1) / fi n : values set to timer ai registers high-order address ?cycle time (2 8 -1) x (m+1) / fi m : values set to timer ai registers low-order address count start condition ?external trigger is input ?the timer overflows ?the count start flag is set (= 1) count stop condition ?the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l tai in pin function programmable i/o port or trigger input tai out pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ?when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ?when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) t i m e r a i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 t o 4 )0 3 9 6 1 6 t o 0 3 9 a 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7 b 6b 5b 4b 3 b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 1 1 : p w m m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 m r 2 m r 1 m r 3 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 b 7 b 6 t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t w r 11 1 1 ( m u s t a l w a y s b e f i x e d t o 1 i n p w m m o d e ) 1 6 / 8 - b i t p w m m o d e s e l e c t b i t 0 : f u n c t i o n s a s a 1 6 - b i t p u l s e w i d t h m o d u l a t o r 1 : f u n c t i o n s a s a n 8 - b i t p u l s e w i d t h m o d u l a t o r t r i g g e r s e l e c t b i t e x t e r n a l t r i g g e r s e l e c t b i t ( n o t e 1 ) 0 : f a l l i n g e d g e o f t a i i n p i n ' s i n p u t s i g n a l ( n o t e 2 ) 1 : r i s i n g e d g e o f t a i i n p i n ' s i n p u t s i g n a l ( n o t e 2 ) 0 : c o u n t s t a r t f l a g i s v a l i d 1 : s e l e c t e d b y e v e n t / t r i g g e r s e l e c t r e g i s t e r n o t e 1 : v a l i d o n l y w h e n t h e t a i i n p i n i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) . i f t i m e r o v e r f l o w i s s e l e c t e d , t h i s b i t c a n b e 1 o r 0 n o t e 2 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 .
81 timera m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 64. example of how a 16-bit pulse width modulator operates figure 65. example of how an 8-bit pulse width modulator operates f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) trigger is not generated by this signal count source condition : reload register = 0003 16 , when external trigger (falling edge of ta0 in pin's input signal) is selected. 1 / f i x (2 ?) 16 ta0 in pin's input signal pwm pulse output from ta0 out pin ? ? ? ? timer a0 interrupt request bit ? ? cleared to ??by software, or when interrupt request is accepted. note: n = 0000 16 to fffe 16 . 1 / f i x n c o u n t s o u r c e ( n o t e 1 ) t a 0 i n p i n ' s i n p u t s i g n a l u n d e r f l o w s i g n a l o f 8 - b i t p r e s c a l e r ( n o t e 2 ) p w m p u l s e o u t p u t f r o m t a 0 o u t p i n h h l l t i m e r a 0 i n t e r r u p t r e q u e s t b i t f i : f r e q u e n c y o f c o u n t s o u r c e ( f 1 , f 8 , f 3 2 , f c 3 2 ) n o t e 1 : t h e 8 - b i t p r e s c a l e r c o u n t s t h e c o u n t s o u r c e . n o t e 2 : t h e 8 - b i t p u l s e w i d t h m o d u l a t o r c o u n t s t h e 8 - b i t p r e s c a l e r ' s u n d e r f l o w s i g n a l . n o t e 3 : m = 0 0 1 6 t o f e 1 6 ; n = 0 0 1 6 t o f e 1 6 . c o n d i t i o n : r e l o a d r e g i s t e r ' s h i g h - o r d e r 8 b i t s = 0 2 1 6 r e l o a d r e g i s t e r ' s l o w - o r d e r b i t s 8 = 0 2 1 6 w h e n e x t e r n a l t r i g g e r ( f a l l i n g e d g e o f t a 0 i n p i n ' s i n p u t s i g n a l ) i s s e l e c t e d . 1 / f i x ( m + 1 ) x ( 2 1 ) 8 1 / f i x ( m + 1 ) x n 1 / f i x ( m + 1 ) c l e a r e d t o 0 b y s o f t w a r e , o r w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d . h l 1 0
82 timerb m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r timer b figure 66 shows the block diagram of timer b. figures 67 and 68 show the timer b-related registers. use the timer bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. figure 66. block diagram of timer b clock source selection (address 0380 16 ) ?event counter ?timer ?pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = i - 1. note, however, j = 2 when i = 0) can be selected in only event counter mode count start flag fc 32 polarity switching and edge pulse (i = 0 to 2) counter reset circuit counter (16) tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 16 0392 16 timer b0 timer b2 0395 16 0394 16 timer b1 tbi in t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t s y m b o l b i t n a m e f u n c t i o n w r b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : t i m e r m o d e 0 1 : e v e n t c o u n t e r m o d e 1 0 : p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e 1 1 : i n h i b i t e d b 1 b 0 t c k 1 m r 3 m r 2 m r 1 t m o d 1 m r 0 t m o d 0 t c k 0 f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e c o u n t s o u r c e s e l e c t b i t ( f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e ) o p e r a t i o n m o d e s e l e c t b i t ( n o t e 1 ) ( n o t e 2 ) n o t e 1 : t i m e r b 0 . n o t e 2 : t i m e r b 1 , t i m e r b 2 . figure 67. timer b-related registers (1)
83 timerb m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 68. timer b-related registers (2) s y m b o la d d r e s sw h e n r e s e t t a b s r0 3 8 0 1 6 0 0 1 6 c o u n t s t a r t f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 t i m e r b 2 c o u n t s t a r t f l a g t i m e r b 1 c o u n t s t a r t f l a g t i m e r b 0 c o u n t s t a r t f l a g t i m e r a 4 c o u n t s t a r t f l a g t i m e r a 3 c o u n t s t a r t f l a g t i m e r a 2 c o u n t s t a r t f l a g t i m e r a 1 c o u n t s t a r t f l a g t i m e r a 0 c o u n t s t a r t f l a g 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g t b 2 s t b 1 s t b 0 s t a 4 s t a 3 s t a 2 s t a 1 s t a 0 s s y m b o la d d r e s sw h e n r e s e t c p s r f0 3 8 1 1 6 0 x x x x x x x 2 c l o c k p r e s c a l e r r e s e t f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 c l o c k p r e s c a l e r r e s e t f l a g 0 : n o e f f e c t 1 : p r e s c a l e r i s r e s e t ( w h e n r e a d , t h e v a l u e i s 0 ) c p s r s y m b o la d d r e s sw h e n r e s e t t b 00 3 9 1 1 6 , 0 3 9 0 1 6 i n d e t e r m i n a t e t b 10 3 9 3 1 6 , 0 3 9 2 1 6 i n d e t e r m i n a t e t b 20 3 9 5 1 6 , 0 3 9 4 1 6 i n d e t e r m i n a t e b 7b 0b 7b 0 ( b 1 5 )( b 8 ) t i m e r b i r e g i s t e r ( n o t e ) w r p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e m e a s u r e s a p u l s e p e r i o d o r w i d t h t i m e r m o d e0 0 0 0 1 6 t o f f f f 1 6 c o u n t s t h e t i m e r ' s p e r i o d f u n c t i o n v a l u e s t h a t c a n b e s e t e v e n t c o u n t e r m o d e0 0 0 0 1 6 t o f f f f 1 6 c o u n t s e x t e r n a l p u l s e s i n p u t o r a t i m e r o v e r f l o w n o t e : r e a d a n d w r i t e d a t a i n 1 6 - b i t u n i t s . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e .
84 timerb m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item specification count source f 1 , f 8 , f 32 , f c32 count operation ?counts down ?when the timer underflows, the reload register's content is reloaded and the timer starts over again. divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ?when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (1) timer mode in this mode, the timer counts an internally generated count source. (see table 21.) figure 69 shows the timer bi mode register in timer mode. table 21. timer specifications in timer mode figure 69. timer bi mode register in timer mode n o t e 1 : t i m e r b 0 . n o t e 2 : t i m e r b 1 , t i m e r b 2 . t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 0 : t i m e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 i n v a l i d i n t i m e r m o d e c a n b e 0 o r 1 m r 2 m r 1 m r 3 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t 0 i n v a l i d i n t i m e r m o d e . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d i n t i m e r m o d e , t u r n s o u t t o b e i n d e t e r m i n a t e . 0 0 ( f i x e d t o 0 i n t i m e r m o d e ; i = 0 ) n o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . ( n o t e 1 ) ( n o t e 2 ) b 7 b 6
85 timerb m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 70. timer bi mode register in event counter mode (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 22.) figure 70 shows the timer bi mode register in event counter mode. table 22. timer specifications in event counter mode item specification count source ?external signals input to tbi in pin ?effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software count operation ?counts down ?when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) i nterrupt request generation timing the timer underflows tbi in pin function count source input read from timer count value can be read out by reading timer bi register write to timer ?when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ?when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0c o u n t p o l a r i t y s e l e c t b i t ( n o t e 1 ) m r 2 m r 1 m r 3 i n v a l i d i n e v e n t c o u n t e r m o d e . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d i n e v e n t c o u n t e r m o d e , t u r n s o u t t o b e i n d e t e r m i n a t e . t c k 1 t c k 0 01 0 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e s 0 1 : c o u n t s e x t e r n a l s i g n a l ' s r i s i n g e d g e s 1 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g a n d r i s i n g e d g e s 1 1 : i n h i b i t e d b 3 b 2 n o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . n o t e 1 : v a l i d o n l y w h e n i n p u t f r o m t h e t b i i n p i n i s s e l e c t e d a s t h e e v e n t c l o c k . i f t i m e r ' s o v e r f l o w i s s e l e c t e d , t h i s b i t c a n b e 0 o r 1 . n o t e 2 : t i m e r b 0 . n o t e 3 : t i m e r b 1 , t i m e r b 2 . n o t e 4 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . i n v a l i d i n e v e n t c o u n t e r m o d e . c a n b e 0 o r 1 . e v e n t c l o c k s e l e c t 0 : i n p u t f r o m t b i i n p i n ( n o t e 4 ) 1 : t b j o v e r f l o w ( j = i - 1 ; h o w e v e r , j = 2 w h e n i = 0 ) 0 ( f i x e d t o 0 i n e v e n t c o u n t e r m o d e ; i = 0 ) ( n o t e 2 ) ( n o t e 3 )
86 timerb m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item specification count source f 1 , f 8 , f 32 , f c32 count operation ?up count ?counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ?when measurement pulse's effective edge is input (note 1) ?when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbi in pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the timer. (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 23.) figure 71 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 72 shows the operation timing when measuring a pulse period. figure 73 shows the operation timing when measuring a pulse width. table 23. timer specifications in pulse period/pulse width measurement mode figure 71. timer bi mode register in pulse period/pulse width measurement mode t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t n a m e b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 1 0 : p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 m e a s u r e m e n t m o d e s e l e c t b i t m r 2 m r 1 m r 3 t c k 1 t c k 0 0 1 0 0 : p u l s e p e r i o d m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s f a l l i n g e d g e t o f a l l i n g e d g e ) 0 1 : p u l s e p e r i o d m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s r i s i n g e d g e t o r i s i n g e d g e ) 1 0 : p u l s e w i d t h m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s f a l l i n g e d g e t o r i s i n g e d g e , a n d b e t w e e n r i s i n g e d g e t o f a l l i n g e d g e ) 1 1 : i n h i b i t e d f u n c t i o n b 3 b 2 n o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d i n e v e n t c o u n t e r m o d e , t u r n s o u t t o b e i n d e t e r m i n a t e . c o u n t s o u r c e s e l e c t b i t t i m e r b i o v e r f l o w f l a g ( n o t e 1 ) 0 : t i m e r d i d n o t o v e r f l o w 1 : t i m e r h a s o v e r f l o w e d 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 b 7 b 6 n o t e 1 : t h e t i m e r b i o v e r f l o w f l a g c h a n g e s t o 0 w h e n t h e c o u n t s t a r t f l a g i s 1 a n d a v a l u e i s w r i t t e n t o t h e t i m e r b i m o d e r e g i s t e r . t h i s f l a g c a n n o t b e s e t t o 1 b y s o f t w a r e . n o t e 2 : t i m e r b 0 . n o t e 3 : t i m e r b 1 , t i m e r b 2 . 0 ( f i x e d t o 0 i n p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e ; i = 0 ) ( n o t e 2 ) ( n o t e 3 )
87 timerb m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 73. operation timing when measuring a pulse width figure 72. operation timing when measuring a pulse period count source measurement pulse count start flag timer bi interrupt request bit timing when counter reaches ?000 16 ? ? transfer (indeterminate value) reload register counter transfer timing ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) measurement of puls time interval from falling edge to falling edge (note 2) cleared to ??by software, or when interrupt request is accepted. transfer (measured value) ? measurement pulse ? count source reload register counter transfer timing count start flag timer bi interrupt request bit timing when counter reaches 0000 16 ? ? ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) (note 1) cleared to ??by software, or when interrupt request is accepted. (note 2) transfer (measured value) transfer (indeterminate value)
88 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 74. block diagram of uarti (i = 0, 1) serial i/o serial i/o is configured as two channels: uart0 and uart1. uart0 and uart1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 74 shows the block diagram of uart0 and uart1. figure 75 shows the block diagram of the transmit/receive unit. uarti (i=0, 1) has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 and 03a8 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few function are different, uart0 and uart1 have almost same functions. figures 76 through 78 show the registers related to uarti. m: values set to uart0 bit rate generator (u0brg) n : values set to u art1 bit rate g enerator (u 1br g) rxd 0 1 / (m+1) 1/16 1/16 1/2 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection cts 0 / rts 0 f 1 f 8 f 32 internal external vcc rts0 cts0 txd 0 transmit/ receive unit rxd 1 1 / (n+1) 1/16 1/16 1/2 bit rate generator (address 03a9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 1 clock source selection f 1 f 8 f 32 internal external rts 1 cts 1 txd 1 (uart1) (uart0) polarity reversing circuit polarity reversing circuit cts/rts disabled clock output pin select switch cts 1 / rts 1 clks 1 cts/rts disabled cts/rts selected cts/rts disabled v cc cts/rts disabled reception control circuit transmission control circuit reception control circuit transmission control circuit transmit/ receive unit
89 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 75. block diagram of transmit/receive unit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronouss type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit 0000000 sp sp par "0" data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8
90 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 76. serial i/o-related registers (1) b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmission data symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate uarti bit rate generator b7 b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate function assuming that set value = n, brgi divides the count source by (n + 1) 00 16 to ff 16 values that can be set symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate b7 b0 (b15) (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note: bits 15 through 12 are set to ??when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 and 03a8 16 ) are set to ?00 2 ?or the receive enable bit is set to ?? (bit 15 is set to ??when bits 14 to 12 all are set to ??) bits 14 and 13 are also set to ??when the lower byte of the uarti receive buffer register (addresses 03a6 16 and 03ae 16 ) is read out. invalid invalid invalid oer fer per sum overrun error flag (note) framing error flag (note) parity error flag (note) error sum flag (note) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found reception data w r w r w r reception data nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ??
91 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 77. serial i/o-related registers (2) w r u a r t i t r a n s m i t / r e c e i v e m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t u i m r ( i = 0 , 1 )0 3 a 0 1 6 , 0 3 a 8 1 6 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e b i t s y m b o l m u s t b e f i x e d t o 0 0 1 0 0 0 : s e r i a l i / o i n v a l i d 0 1 0 : i n h i b i t e d 0 1 1 : i n h i b i t e d 1 1 1 : i n h i b i t e d b 2 b 1 b 0 c k d i r s m d 1 s m d 0 s e r i a l i / o m o d e s e l e c t b i t s m d 2 i n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t s t p s p r y p r y e s l e p p a r i t y e n a b l e b i t 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k s t o p b i t l e n g t h s e l e c t b i t o d d / e v e n p a r i t y s e l e c t b i t s l e e p s e l e c t b i t 0 : o n e s t o p b i t 1 : t w o s t o p b i t s 0 : p a r i t y d i s a b l e d 1 : p a r i t y e n a b l e d 0 : s l e e p m o d e d e s e l e c t e d 1 : s l e e p m o d e s e l e c t e d 1 0 0 : t r a n s f e r d a t a 7 b i t s l o n g 1 0 1 : t r a n s f e r d a t a 8 b i t s l o n g 1 1 0 : t r a n s f e r d a t a 9 b i t s l o n g 0 0 0 : s e r i a l i / o i n v a l i d 0 1 0 : i n h i b i t e d 0 1 1 : i n h i b i t e d 1 1 1 : i n h i b i t e d b 2 b 1 b 0 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k i n v a l i d v a l i d w h e n b i t 6 = 1 0 : o d d p a r i t y 1 : e v e n p a r i t y i n v a l i d i n v a l i d m u s t a l w a y s b e 0 f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) u a r t i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 s y m b o la d d r e s sw h e n r e s e t u i c 0 ( i = 0 , 1 )0 3 a 4 1 6 , 0 3 a c 1 6 0 8 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) t x e p t c l k 1 c l k 0 c r s c r d n c h c k p o l b r g c o u n t s o u r c e s e l e c t b i t t r a n s m i t r e g i s t e r e m p t y f l a g 0 : t r a n s m i t d a t a i s o u t p u t a t f a l l i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t r i s i n g e d g e 1 : t r a n s m i t d a t a i s o u t p u t a t r i s i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t f a l l i n g e d g e c l k p o l a r i t y s e l e c t b i t c t s / r t s f u n c t i o n s e l e c t b i t c t s / r t s d i s a b l e b i t d a t a o u t p u t s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 0 : l s b f i r s t 1 : m s b f i r s t 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) 0 : c t s / r t s f u n c t i o n e n a b l e d 1 : c t s / r t s f u n c t i o n d i s a b l e d ( p 4 7 a n d p 7 4 f u n c t i o n a s p r o g r a m m a b l e i / o p o r t ) 0 : t x d i p i n i s c m o s o u t p u t 1 : t x d i p i n i s n - c h a n n e l o p e n - d r a i n o u t p u t u f o r mt r a n s f e r f o r m a t s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 v a l i d w h e n b i t 4 = 0 0 : c t s f u n c t i o n i s s e l e c t e d ( n o t e 1 ) 1 : r t s f u n c t i o n i s s e l e c t e d ( n o t e 2 ) v a l i d w h e n b i t 4 = 0 0 : c t s f u n c t i o n i s s e l e c t e d ( n o t e 1 ) 1 : r t s f u n c t i o n i s s e l e c t e d ( n o t e 2 ) 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) 0 : t x d i p i n i s c m o s o u t p u t 1 : t x d i p i n i s n - c h a n n e l o p e n - d r a i n o u t p u t m u s t a l w a y s b e 0 b i t n a m e b i t s y m b o l m u s t a l w a y s b e 0 n o t e 1 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . n o t e 2 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . 0 : c t s / r t s f u n c t i o n e n a b l e d 1 : c t s / r t s f u n c t i o n d i s a b l e d ( p 4 7 a n d p 7 7 f u n c t i o n a s p r o g r a m m a b l e i / o p o r t ) w r
92 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 78. serial i/o-related registers (3) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register note: when using multiple pins to output the transfer clock, the following requirement must be met: ?uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? u0irs u1irs u0rrm u1rrm invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = ?? 0 : clock output to clk1 1 : clock output to clks1 reserved bit must always be ? must always be ? nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be ?? 0
93 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. table 24 lists the specifications of the clock synchronous serial i/o mode. figure 79 shows the uarti transmit/receive mode register. table 24. specifications of clock synchronous serial i/o mode specification ? transfer data length: 8 bits ? when internal clock is selected (bit 3 at address 03a0 16 , 03a8 16 = 0) : fi/ 2(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at address 03a0 16 , 03a8 16 =1) : input from clki pin (note 2) _______ ________ _______ ________ ? cts function/ rts function/ cts,rts function chosen to be invalid ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at address 03a5 16 , 03ad 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 ) = 0 _______ _______ _ when cts function is selected, cts input level = "l" ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at address 03a4 16 , 03ac 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at address 03a4 16 , 03ac 16 ) = 1: clki input level = l ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at address 03a5 16 , 03ad 16 ) = 1 _ transmit enable bit (bit 0 at address 03a5 16 , 03ad 16 ) = 1 _ transmit buffer empty flag (bit 1 at address 03a5 16 , 03ad 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at address 03a4 16 , 03ac 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at address 03a4 16 , 03ac 16 ) = 1: clki input level = l ? when transmitting _ transmit interrupt cause select bit (bits 0,1 at address 03b0 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bits 0,1 at address 03b0 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti re- ceive buffer register are read out ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection uart1 transfer clock can be set 2 pins, and can be selected to output from which pin. note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: maximum 5 mbps. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. item transfer data format transfer clock transmission/reception control transmission start condi- tion reception start condition interrupt request generation timing error detection select function
94 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 79. uarti transmit/receive mode register in clock synchronous serial i/o mode (i=0,1) table 25 lists the functions of the input/output pins during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table 25. input/output pin functions in clock synchronous serial i/o mode (i=0,1) symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode register internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be "0" in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode pin name function method of selection txdi (p4 4 , p7 4 ) serial data output serial data input transfer clock output transfer clock input programmable i/o port (outputs dummy data when performing reception only) rxdi (p4 5 , p7 5 ) clki (p4 6 , p7 6 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ? port p4 6 , p7 6 direction register (bits 6 at address 03ea 16 and 03ef 16 ) = ? port p4 5 , p7 5 direction register (bits 5 at address 03ea 16 and 03ef 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) =?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 ) = ?? port p4 7 , p7 7 direction register (bits 7 address 03ea 16 and 03ef16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) = ?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) = ? cts input rts output ctsi/rtsi (p4 7 , p7 7 )
95 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 80. typical transmit/receive timings in clock synchronous serial i/o mode ?example of transmit timing (when internal clock is selected) ?example of receive timing (when external clock is selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t c t c l k s t o p p e d p u l s i n g b e c a u s e t r a n s f e r e n a b l e b i t = 0 d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r t c = t c l k = 2 ( n + 1 ) / f i f i : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( f 1 , f 8 , f 3 2 ) n : v a l u e s e t t o b r g i t r a n s f e r c l o c k t r a n s m i t e n a b l e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t l ) c l k i t x d i t r a n s m i t r e g i s t e r e m p t y f l a g ( t x e p t ) h l 0 1 0 1 0 1 c t s i s h o w n i n ( ) a r e b i t s y m b o l s . t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : i n t e r n a l c l o c k i s s e l e c t e d . c t s f u n c t i o n i s s e l e c t e d . c l k p o l a r i t y s e l e c t b i t = 0 . t r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t = 0 . t r a n s m i t i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . s t o p p e d p u l s i n g b e c a u s e c t s = h 1 / f e x t d u m m y d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r t r a n s m i t e n a b l e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t l ) c l k i r x d i r e c e i v e c o m p l e t e f l a g ( r l ) r t s i h l 0 1 0 1 0 1 r e c e i v e e n a b l e b i t ( r e ) 0 1 r e c e i v e d a t a i s t a k e n i n t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r r e a d o u t f r o m u a r t i r e c e i v e b u f f e r r e g i s t e r s h o w n i n ( ) a r e b i t s y m b o l s . t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s . e x t e r n a l c l o c k i s s e l e c t e d . r t s f u n c t i o n i s s e l e c t e d . c l k p o l a r i t y s e l e c t b i t = 0 . f e x t : f r e q u e n c y o f e x t e r n a l c l o c k t r a n s f e r r e d f r o m u a r t i r e c e i v e r e g i s t e r t o u a r t i r e c e i v e b u f f e r r e g i s t e r r e c e i v e i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . m e e t t h e f o l l o w i n g c o n d i t i o n s w h e n t h e c l k i n p u t b e f o r e d a t a r e c e p t i o n = h t r a n s m i t e n a b l e b i t 1 r e c e i v e e n a b l e b i t 1 d u m m y d a t a w r i t e t o u a r t i t r a n s m i t b u f f e r r e g i s t e r
96 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (a) polarity select function as shown in figure 81, the clk polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 ) allows selection of the polarity of the transfer clock. figure 81. polarity of transfer clock (b) lsb first/msb first sel82ga-9, when the transfer format select bit (bit 7 at addresses 03a4 16 , 03ac 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 82. transfer format ?when clk polarity select bit = ? note 2: the clki pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ?when clk polarity select bit = ? note 1: the clki pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i lsb first ?when transfer format select bit = ? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i ?when transfer format select bit = ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 t x d i r x d i clk i msb first note: this applies when the clk polarit y select bit = ??
97 serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (c) transfer clock output from multiple pins function this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure 83.) the multiple pins function is valid only when the internal clock is selected for uart1. note that when this _______ _______ function is selected, cts/rts function of uart1 cannot be used. figure 83. the transfer clock output from the multiple pins function usage (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. microcomputer t x d 1 (p7 4 ) clks 1 (p7 7 ) clk 1 (p7 6 ) in clk in clk note: this applies when the internal clock is selected and transmission is p erformed only in clock synchronous serial i/o mode.
98 clock asynchronous serial i/o (uart) mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (2) clock asynchronous serial i/o (uart) mode the uart allows transmitting and receiving data after setting the desired transfer rate and transfer data format. table 26 lists the specifications of the uart mode. figure 84 shows the uarti transmit/receive mode register. table 26. specifications of clock synchronous serial i/o mode item specification transfer data format ?character bit (transfer data): 7 bits, 8 bits or 9 bits as selected ?start bit: 1 bit ?parity bit: odd, even or nothing as selected ?stop bit: 1 bit or 2 bits as selected transfer clock ?when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 = 0) : fi/16(n+1) (note 1) fi = f 1 , f 8 , f 32 ?when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 =1) : f ext /16(n+1) (note 1) (note 2) transmission/reception control _______ _______ _______ _______ ?cts function/rts function/cts, rts function chosen to be invalid transmission start condition ?to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 ) = 0 _______ _______ - when cts function is selected, cts input level = l reception start condition ?to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 ) = 1 - start bit detection interrupt request ?when transmitting generation timing - transmit interrupt cause select bits (bits 0,1 at address 03b0 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ?when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ?overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ?framing error this error occurs when the number of stop bits set is not detected ?parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ?error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function ?sleep mode selection this mode is used to transfer data to and from one of multiple slave microcomputers note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1.
99 clock asynchronous serial i/o (uart) mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 27 lists the functions of the input/output pins during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n- channel open-drain is selected, this pin is in floating state.) table 27. input/output pin functions in uart mode (i=0,1) figure 84. uarti transmit/receive mode register in uart mode pin name function method of selection txdi (p4 4 , p7 4 ) serial data output serial data input programmable i/o port transfer clock input programmable i/o port rxdi (p4 5 , p7 5 ) clki (p4 6 , p7 6 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ?? port p4 5 , p7 5 direction register (bits 5 at address 03ea 16 and 03ef 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) =?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 ) = ?? port p4 7 , p7 7 direction register (bits 7 at address 03ea 16 and 03ef 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) = ?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) = ? cts input rts output ctsi/rtsi (p4 7 , p7 7 ) (outputs dummy data when performing reception only) symbol address when reset uimr (i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode register internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd/even parity select bit parity enable bit sleep select bit
100 clock asynchronous serial i/o (uart) mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ?example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ?example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 85. typical transmit timings in uart mode t r a n s m i t e n a b l e e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t i ) t r a n s m i t r e g i s t e r e m p t y f l a g ( t x e p t ) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s t p s t a r t b i t p a r i t y b i t t x d i c t s i t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : p a r i t y i s e n a b l e d . o n e s t o p b i t . c t s f u n c t i o n i s s e l e c t e d . t r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t = 1 . 1 0 1 l h 0 1 t c = 1 6 ( n + 1 ) / f i o r 1 6 ( n + 1 ) / f e x t f i : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( f 1 , f 8 , f 3 2 ) f e x t : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( e x t e r n a l c l o c k ) n : v a l u e s e t t o b r g i t r a n s m i t i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s t p s p d 0 d 1 s t t r a n s m i t e n a b l e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t i ) t x d i t r a n s m i t r e g i s t e r e m p t y f l a g ( t x e p t ) 0 1 0 1 0 1 t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : p a r i t y i s d i s a b l e d . t w o s t o p b i t s . c t s f u n c t i o n i s d i s a b l e d . t r a n s m i t i n t e r r u p t c a u s e s s e l e c t b i t = 0 . t r a n s f e r c l o c k t c t c = 1 6 ( n + 1 ) / f i o r 1 6 ( n + 1 ) / f e x t f i : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( f 1 , f 8 , f 3 2 ) f e x t : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( e x t e r n a l c l o c k ) n : v a l u e s e t t o b r g i t r a n s m i t i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 s h o w n i n ( ) a r e b i t s y m b o l s . s h o w n i n ( ) a r e b i t s y m b o l s . t c t r a n s f e r c l o c k s p s t o p p e d p u l s i n g b e c a u s e t r a n s m i t e n a b l e b i t = 0 s t o p b i t t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r s t a r t b i t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s td 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s t d 8 d 0 d 1 s t s p s p s t o p b i t s p t h e t r a n s f e r c l o c k s t o p s m o m e n t a r i l y a s c t s i s h w h e n t h e s t o p b i t i s c h e c k e d . t h e t r a n s f e r c l o c k s t a r t s a s t h e t r a n s f e r s t a r t s i m m e d i a t e l y c t s c h a n g e s t o l . d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r s p t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r s t o p b i t d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r . 0 c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d .
101 clock asynchronous serial i/o (uart) mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ?example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 86. typical receive timing in uart mode (a) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers d 0 d 1 s t a r t b i t s a m p l e d l r e c e i v e d a t a t a k e n i n b r g i ' s c o u n t s o u r c e r e c e i v e e n a b l e b i t r x d i t r a n s f e r c l o c k r e c e i v e c o m p l e t e f l a g r t s i s t o p b i t 1 0 0 1 h l t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : p a r i t y i s d i s a b l e d . o n e s t o p b i t . r t s f u n c t i o n i s s e l e c t e d . r e c e i v e i n t e r r u p t r e q u e s t b i t 0 1 c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . t r a n s f e r r e d f r o m u a r t i r e c e i v e r e g i s t e r t o u a r t i r e c e i v e b u f f e r r e g i s t e r r e c e p t i o n t r i g g e r e d w h e n t r a n s f e r c l o c k i s g e n e l a t e d b y f a l l i n g e d g e o f s t a r t b i t d 7 connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0.
102 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r serial i/o2 serial i/o2 is used as the clock synchronous serial i/o and has an ordinary mode and an automatic transfer mode. in the automatic transfer mode, serial transfer is performed through the serial i/o automatic transfer ram which has up to 256 bytes (addresses 00400 16 to 004ff 16 ). the s rdy2 , s busy2 and s stb2 pins each have a handshake i/o signal function and can select either h active or l active for active logic. specification ? 8-bit serial i/o mode (non-automatic transfer) ? automatic transfer serial i/o mode ? transfer data length: 8 bits ? full duplex mode / transmit-only mode selected by bit 5 at address 0342 16 ? when internal clock is selected (bit 2 at address 0342 16 = 0) : selected by bits 5 to 7 at address 0348 16 ? when external clock is selected (bit 2 at address 034216 = 1) : input from s clk21 pin, s clk22 pin(note 2) ? when internal clock is selected : f(x in )/4, f(x in )/8, f(x in )/16, f(x in )/32, f(x in )/64, f(x in )/128, f(x in )/256 ? when external clock is selected : input cycle 0.95 m s or less ? s stb2 output / s busy2 input or output / s rdy2 input or output chosen ? to start transmission / reception, the following requirements must be met: _ serial i/o initialization bit (bit 4 at address 0342 16 ) = 1 _ when s busy2 input, or s rdy2 input is selected : selected input level = h ____________ _________ _ when s busy2 input, or s rdy2 input is selected : selected input level = l ? furthermore, if external clock is selected, the following requirements must also be met: _ input level of s clk21 or s clk22 = h ? to stop transmission and reception, set serial i/o initialization bit (bit 4 at address 0342 16 ) to 0 regardless internal clock and external clock. ? 8-bit serial i/o mode : interrupts requested when 8-bit data transfer is com- pleted ? automatic transfer serial i/o mode :interrupts requested when last receive data transfer to automatic transfer ram ? s out2 p-channel output disable function cmos output or n-channel open-drain output can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? serial i/o2 clock pin select bit serial clock input/output can be selected; s clk21 or s clk22 ? s busy output, s stb2 output select function (only automatic transfer serial mode) s busy output, s stb2 output can be selected; 1-byte data transfer unit or all data transfer unit ? s out2 pin control bit either output active or high-impedance can be selected as a s out2 pin state at serial non-transfer . note 1: it is necessary to set the serial i/o clock pin select bit ( bit 7 at address 0342 16 ) item serial mode transfer data format transfer clock transfer rate transmission/reception control transmission / reception start condition transmission and reception stop condition interrupt request generation timing select function table 28. specifications of clock synchronous serial i/o2
103 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 87. block diagram of serial i/o2 main data bus serial i/o2 automatic transfer controller local data bus serial i/o automatic transfer ram (00400 16 ?04ff 16 ) serial i/o2 control register 3 x in serial i/o2 automatic transfer data pointer address decoder main address bus local address bus 1/8 1/16 1/32 1/64 1/128 serial i/o2 interrupt request port latch serial i/o2 counter synchronous circuit serial i/o2 synchronous clock selection bit ? port latch s clk21 ? ? s clk2 ? internal synchronous clock selection bits 1/256 port latch s busy2 s stb2 (s stb2 pin control bit) serial transfer status flag ? ? ? ? ? ? port latch s out2 s in2 port latch serial i/o2 register (8) ? ? serial transfer selection bits divider 1/4 serial i/o2 clock pin selection bit s clk22 ? ? port latch ? ? ? ? serial i/o2 clock pin selection bits s rdy2 s rdy2 ? busy2 pin control bit s rdy2 ? busy2 pin control bit
104 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 88. serial i/o2 control registers 1, 2 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 s y m b o la d d r e s sw h e n r e s e t s i o 2 c o n 20 3 4 4 1 6 0 0 1 6 b i t n a m ef u n c t i o n r b i t s y m b o l w b 7b 6b 5b 4 b 3b 2b 1b 0 s r d y 2 s b u s y 2 p i n c o n t r o l b i t s s c o n 2 0 s c o n 2 1 s c o n 2 2 s c o n 2 3 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s y m b o la d d r e s sw h e n r e s e t s i o 2 c o n 10 3 4 2 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l r w b 7b 6b 5b 4b 3b 2b 1b 0 s e r i a l t r a n s f e r s e l e c t b i t s s c o n 1 0 s c o n 1 1 s c o n 1 2 s c o n 1 3 s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t b i t s ( s s t b 2 p i n c o n t r o l b i t ) 0 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) 0 1 : e x t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) 1 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n s s t b 2 o u t p u t . ) 1 1 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n s s t b 2 o u t p u t . ) 0 : s e r i a l i / o i n i t i a l i z a t i o n 1 : s e r i a l i / o e n a b l e d s e r i a l i / o i n i t i a l i z a t i o n b i t t r a n s f e r m o d e s e l e c t b i t 0 : f u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e ( s i n 2 p i n i s a s i n 2 i n p u t . ) 1 : t r a n s m i t - o n l y m o d e ( s i n 2 p i n i s a n i / o p o r t . ) s c o n 1 4 s c o n 1 5 s e r i a l i / o 2 c l o c k p i n s e l e c t b i t t r a n s f e r d i r e c t i o n s e l e c t b i t s c o n 1 6 s c o n 1 7 0 0 : s e r i a l i / o d i s a b l e d ( s e r i a l i / o p i n s a r e i / o p o r t s ) 0 1 : 8 - b i t s s e r i a l i / o 1 0 : i n h i b i t 1 1 : a u t o m a t i c t r a n s f e r s e r i a l i / o ( 8 - b i t s ) 0 : l s b f i r s t 1 : m s b f i r s t 0 : s c l k 2 1 ( s c l k 2 2 p i n i s a n i / o p o r t . ) 1 : s c l k 2 2 ( s c l k 2 1 p i n i s a n i / o p o r t . ) 0 : f u n c t i o n s a s e a c h 1 - b y t e s i g n a l 1 : f u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a s b u s y 2 o u t p u t s s t b 2 o u t p u t f u n c t i o n s e l e c t b i t ( v a l i d i n a u t o m a t i c t r a n s f e r m o d e ) s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g s c o n 2 4 s c o n 2 5 s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t s o u t 2 p i n c o n t r o l b i t ( a t n o - t r a n s f e r s e r i a l d a t a ) s c o n 2 6 s c o n 2 7 0 : o u t p u t a c t i v e 1 : o u t p u t h i g h - i m p e d a n c e 0 : c m o s 3 - s t a t e ( p - c h a n n e l o u t p u t i s v a l i d . ) 1 : n - c h a n n e l o p e n - d r a i n ( p - c h a n n e l o u t p u t i s i n v a l i d . ) b 3 b 2 b 1 b 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 s r d y 2 p i ns b u s y 2 p i n i / o p o r ti / o p o r t n o t u s e d s r d y 2 o u t p u ti / o p o r t s r d y 2 o u t p u ti / o p o r t i / o p o r ts b u s y 2 i n p u t i / o p o r ts b u s y 2 i n p u t i / o p o r ts b u s y 2 o u t p u t i / o p o r ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t b 1 b 0 b 3 b 2
105 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 89. serial i/o2 automatic transfer data pointer serial i/o2 control register 3 symbol address when reset sio2con3 0348 16 00000000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 automatic transfer interval set bits ttran0 ttran1 ttran2 ttran3 internal synchronous clock selection bits 000:f(x in )/4 001:f(x in )/8 010:f(x in )/16 011:f(x in )/32 100:f(x in )/64 101:f(x in )/128 110:f(x in )/256 ttran4 tclk0 tclk1 tclk2 00000 :2 cycles of transfer clocks 00001 :3 cycles of transfer clocks : 11110 :32 cycles of transfer clocks 11111 :33 cycles of transfer clocks data is written to a latch and read from a decrement counter. b4b3b2b1b0 b7b6b5 serial i/o2 automatic transfer data pointer symbol address when reset sio2dp 0340 16 00 16 function r w b7 b6 b5 b4 b3 b2 b1 b0 ?automatic transfer data pointer set specify the low-order 8 bits of the first data store address on the serial i/o automatic transfer ram. data is written into the latch and read from the decrement counter. serial i/o2 register/transfer counter symbol address when reset sio2 0346 16 00 16 function r w b7 b6 b5 b4 b3 b2 b1 b0 ?number of automatic transfer data set set the number of automatic transfer data. set a value one less than number of transfer data. data is written into the latch and read from the decrement counter.
106 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 29. functions of the serial i/o2 input/output pins table 29 lists the functions of the serial i/o2 input/output pins pin name function method of selection s out2 (p9 4 ) serial data output serial data input transfer clock output transfer clock input port p9 4 direction register (bit 4 at address 03f3 16 )= ?? s out2 p-channel output disable bit (bit 7 at address 0344 16 )= ??, ?? s out2 pin control bit (bit 6 at address 0344 16 )= ??, ?? (outputs dummy data when performing reception only) s in2 (p9 3 ) s clk21 (p9 5 ) serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?0?, ?1 serial i/o2 clock pin select bit (bit 7 at address 0342 16 ) = ? serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?1?, ?1 serial i/o2 clock pin select bit (bit 7 at address 0342 16 ) = ? port p9 5 direction register (bit 5 at address 03f3 16 )= ? port p9 3 direction register (bit 4 at address 03f3 16 )= ?? transfer mode select bit (bit 5 at address 0342 16 )= ? (input/output port when transfer mode select bit (bit 5 at address 0342 16 )= ?? transfer clock output transfer clock input s clk22 (p9 6 ) serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?0?, ?1 serial i/o2 clock pin select bit (bit 7 at address 0342 16 ) = ? serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?1?, ?1 serial i/o2 clock pin select bit (bit 7 at address 0342 16 ) = ? port p9 6 direction register (bit 6 at address 03f3 16 )= ? s rdy input / output s rdy2 (p9 0 ) set by s rdy2 ?s busy2 pin control bits (bits 0 to 3 at address 0344 16 ) s busy input / output s busy2 (p9 1 ) set by s rdy2 ?s busy2 pin control bits (bits 0 to 3 at address 0344 16 ) s busy2 output ?s stb2 output function select bit (bit 4 at address 0344 16 )= ??, ? s stb input / output s stb2 (p9 2 ) serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?0?, ?1 s busy2 output ?s stb2 output function select bit (bit 4 at address 0344 16 )= ??, ? s out2 output either output active or high-impedance can be selected as a s out2 pin state at serial non-transfer by the s out2 pin control bit (bit 6 of address 0344 16 ). however, when the external synchronous clock is selected, perform the following setup to put the s out2 pin into a high-impedance state. when the s clk2i ( i = 1, 2) input is h after completion of transfer, set the s out2 pin control bit to 1. when the s clk2i ( i = 1, 2) input goes to l after the start of the next serial transfer, the s out2 pin control bit is automatically reset to 0 and put into an output active state.
107 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r serial i/o2 mode there are two types of serial i/o2 modes: 8-bit serial i/o mode where automatic transfer ram is not used, and an automatic transfer serial i/o mode. (1) 8-bit serial i/o mode address 0346 16 is assigned to the serial i/o2 register. when the internal synchronous clock is selected, a serial transfer of the 8-bit serial i/o is started by a write signal to the serial i/o2 register (address 0346 16 ). the serial transfer status flag (bit 5 of address 0344 16 ) is set to 1 by writing into the serial i/o2 register and reset to 0 after completion of 8-bit transfer. at the same time, a serial i/o2 interrupt request occurs. if the transfer is completed, the receive data is read out from serial i/o2 register. when the external synchronous clock is selected, the contents of the serial i/o2 register are con- tinuously shifted while transfer clocks are input to s clk21 or s clk22 . therefore, the clock needs to be controlled externally. (2) automatic transfer serial i/o mode address 0346 16 is assigned to the transfer counter (1-byte units). the serial i/o2 automatic trans- fer controller controls the write and read operations of the serial i/o2 register. the serial i/o auto- matic transfer ram is mapped to addresses 00400 16 to 004ff 16 . before starting transfer, make sure the 8 low-order bits of the address that contains the beginning data to be serially transferred is set to the automatic transfer data pointer (address 0340 16 ). when the internal synchronous clock is selected, the transfer interval is inserted between one data and another in the following cases: 1. when using no handshake signal 2. when using the s rdy2 output, s busy2 output, and s stb2 output of the handshake signal inde pendently 3. when using a combination of s rdy2 output and s stb2 output or a combination of s busy2 output and s stb2 output of the handshake signal the transfer interval can be set in the range of 2 to 23 cycles using the automatic transfer interval set bit (bits 0C4 of address 0348 16 ). also, when using s busy2 output as a signal for each occurrence of the all transfer data, a transfer interval is inserted before the system starts sending or receiving the first data and after the system finished sending or receiving the last data, not just between one data and another. furthermore, when using s stb2 output, the transfer interval between each 1-byte data is extended by 2 cycles from the set value no matter how the s busy2 output. s stb2 output function select bit (bit 4 of address 0344 16 ) is set. when using s busy2 output and s stb2 output in combination as a signal for each occurrence of the all transfer data, the transfer interval after the system finished sending or receiving the last data is extended by 2 cycles from the set value. when an external synchronous clock is selected, the automatic transfer interval is disabled.
108 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 90. automatic transfer serial i/o operation 004ff 16 automatic transfer ram transfer counter automatic transfer data pointer serial i/o2 re g ister 00452 16 00451 16 00450 16 0044f 16 0044e 16 00400 16 04 16 52 16 s in2 s out2 when the internal synchronous clock is selected, automatic serial transfer starts by writing 1 less than the number of transfer bytes to the transfer counter (address 0346 16 ). when an external sync clock is selected, automatic serial transfer starts by writing 1 less than the number of transfer bytes to the transfer counter and the transfer clock is input. in this case, allow for at least 5 cycles of internal system clock before the transfer clock is input after writing to the transfer counter. also, for data to data transfer intervals, allow at least 5 cycles of internal system clock reckoning from a rise of clock at the last bit of one-byte data. regardless of whether the internal or external synchronous clock is selected, the automatic transfer data pointer and the transfer counter are decreased after each 1-byte data is received and then written into the automatic transfer ram. the serial transfer status flag (bit5 of address 0344 16 ) is set to 1 by writing data into the transfer counter. the serial transfer status flag is reset to 0 after the last data is written into the automatic transfer ram. at the same time, a serial i/o2 interrupt request occurs. the values written in the automatic transfer data pointer (address 0340 16 ) and the automatic transfer interval set bits (bit 0 to bit 4 of address 0348 16 ) are held in the latch. when data is written into the transfer counter, the values latched in the automatic transfer data pointer (address 0340 16 ) and the automatic transfer interval set bits (bit 0 to bit 4) are transferred to the decrement counter.
109 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r handshake signal there are five types of handshake signal : s stb2 output, s busy2 input/ output , and s rdy2 input/output. (1) s stb2 output signal the s stb2 output is a signal to inform an end of transmission/reception to the serial transfer destina- tion. the s stb2 output signal can be used only when the internal synchronous clock is selected. in the initial status [ serial i/o initialization bit (bit 4 of address 0342 16 ) = 0 ], the s stb2 output goes to l __________ (bits 2, 3 of address 0342 16 =11), or the s stb2 output goes to h (bits 2, 3 of address 0342 16 =10). at the end of transmit/receive operation, after the all data of the serial i/o2 register ( address 0346 16 ) is _________ output from s out2 , s stb2 output is h (or s stb2 output is l) in the period of 1 cycle of the transfer clock. furthermore, after 1 cycle, the serial transfer status flag (bit 5 of address 0344 16 ) is reset to 0. in the automatic transfer serial i/o mode, whether the s stb2 output is to be output at an end of each 1-byte data or after completion of transfer of all data can be selected by the s busy2 output ? s stb2 output function select bit (bit 4 of address 0344 16 ). figure 91. s stb2 output operation "1" "0" s stb2 (output) "h" "l" d 0 tc d 1 d 2 d 3 d 4 d 5 d 6 d 7 "1" "0" "h" "l" d 0 tc d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 automatic transfer interval ?erial operation used s stb2 output operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock s stb2 output timing : each 1-byte data internal clock serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i=1, 2)(output) s out2 tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 ?erial operation used s stb2 output operation mode : automatic transfer serial i/o mode transfer clock : internal synchronous clock s stb2 output timing : each transfer of all data internal clock serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i=1, 2)(output) s stb2 (output) s out2 tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16
110 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 93. s busy2 input operation (2) figure 92. s busy2 input operation (1) (2) s busy2 input signal the s busy2 input is a signal requested to stop of transmission/reception from the serial transfer des- tination. when the internal synchronous clock is selected, input a h level signal into the s busy2 input (or a l ___________ level signal into the s busy2 input) in the initial status [serial i/o initialization bit (bit 4 of address ____________ 0342 16 ) = 0]. when a l level signal into the s busy2 ( or h on s busy2 ) input for 1.5 cycles or more of transfer clock, transfer clocks are output from s clk2i (i = 1, 2) , and transmit/receive operation is ____________ started. when s busy2 input is driven h (or s busy2 input is driven l) during transmit/receive operation, the transfer clock being output from s clk2i (i = 1, 2) remains active until after the system finishes sending or receiving the designated number of bits, without stopping the transmit/receive operation immediately. the handshake unit of the 8-bit serial i/o is 8 bits, and that of the automatic transfer serial i/o is 8 bits. internal clock "1" "0" "h" "l" tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1.5 cycle or more ?erial operation used s busy2 input operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock s busy2 input timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(output) s out2 s busy2 (input ) tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 "1" "0" "h" "l" note: the last output data d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 invalid note ?erial operation used s busy2 input operation mode : 8-bit serial i/o mode transfer clock : external synchronous clock s busy2 input timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(input ) s out2 s busy2 (input ) high-impedance high-impedance when the external synchronous clock is selected, input a h level signal into the s busy2 input (or a l ___________ level signal into the s busy2 input) in the initial status[serial i/o initialization bit (bit 4 of address 0342 16 ) = 0]. at this time, the transfer clock become invalid. the transfer clock become valid while a l level ___________ signal is input into the s busy2 input (or a h level signal into the s busy2 input) and transmit/receive operation work. ___________ when changing the input values into the s busy2 (or s busy2 ) input at these operations, change them when the transfer clock input is in a h state. when the high-impedance of the s out2 output is selected by the s out2 pin control bit (bit 6 of address 0344 16 ), the s out2 becomes high-impedance, ___________ while a h level signal is input into the s busy2 input (or a l level signal into the s busy2 input.)
111 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 94. s busy2 output operation (1) figure 95. s busy2 output operation (2) internal clock "1" "0" "h" "l" d 0 tc tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ?erial operation used s busy2 output operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock s busy2 output timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s out2 s clk2i (i = 1, 2)(output) s busy2 (output ) "1" "0" "h" "l" d 0 s out2 d 1 d 2 d 3 d 4 d 5 d 6 d 7 write to serial i/o register (address 0346 16 ) ?erial operation used s busy2 output operation mode : 8-bit serial i/o mode transfer clock : external synchronous clock s busy2 output timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(input) s busy2 (output) (3) s busy2 output signal the s busy2 output is a signal which requests to stop of transmission/reception to the serial transfer destination. in the automatic transfer serial i/o mode, regardless of the internal or external synchro- nous clock, whether the s busy2 output is to be output at transfer of each 1-byte data or during transfer of all data can be selected by the s busy2 output ? s stb2 output function select bit (bit 4 of address 0344 16 ). in the initial status[ serial i/o initialization bit (bit 4 of address 0342 16 ) = 0 ], the status in ____________ which the s busy2 outputs h (or the s busy2 outputs l). when the internal synchronous clock is selected, in the 8-bit serial i/o mode and the automatic trans- fer serial i/o mode (s busy2 output function: each 1-byte signal is selected), the s busy2 output goes to ____________ l (or the s busy2 output goes to h) before 0.5 cycle of the timing at which the transfer clock goes to l . in the automatic transfer serial i/o mode (the s busy2 output function: all transfer data is selected), ____________ the s busy2 output goes to l (or the s busy2 output goes to h) when the first transmit data is written into the serial i/o2 register (address 0346 16 ). ____________ when the external synchronous clock is selected, the s busy2 output goes to l (or the s busy2 output goes to h) when transmit data is written into the serial i/o2 register(address 0346 16 ), regardless of the serial i/o transfer mode. at termination of transmit/receive operation, in the 8-bit serial i/o mode, the s busy2 output goes to h ____________ (or the s busy2 output returns to l), when the serial transfer status flag is set to 0, regardless of whether the internal or external synchronous clock is selected. furthermore, in the automatic transfer serial i/o mode (s busy2 output function: each 1-byte signal is selected), the s busy2 output goes to h ____________ (or the s busy2 output goes to l) each time 1-byte of receive data is written into the automatic trans- fer ram.
112 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 96. s busy2 output operation (3) internal clock "1" "0" "h" "l" d 0 tc d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 automatic transfer interval automatic transfer ram serial i/o2 register serial i/o2 register automatic transfer ram ?erial operation used s busy2 output operation mode : automatic transfer serial i/o mode transfer clock : internal synchronous clock s busy2 output timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(output) s out2 tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 s busy2 (output) internal clock "1" "0" "h" "l" d 0 tc d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 automatic transfer interval automatic transfer ram serial i/o2 register serial i/o2 register automatic transfer ram ?erial operation used s busy2 output operation mode : automatic transfer serial i/o mode transfer clock : internal synchronous clock s busy2 output timing : each transfer of all data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(output) s out2 tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 s busy2 (output)
113 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 97. s rdy2 output operation figure 98. s rdy2 input operation ?erial operation used s rdy2 output internal clock s rdy2 (output) "h" "l" tc tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s clk2i (i = 1, 2) (output) s out2 operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock "1" "0" serial transfer status flag (bit 5 at address 0344 16 ) ?erial operation used s rdy2 input internal clock "1" "0" s rdy2 (input ) "h" "l" tc tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1.5 cycle or more s clk2i (i = 1, 2) (output) s out2 operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock serial transfer status flag (bit 5 at address 0344 16 ) (4) s rdy2 output signal the s rdy2 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. in the initial status[serial i/o initialization bit (bit 4 of address 0342 16 ) = 0 ], __________ the s rdy2 output goes to l (or the s rdy2 output goes to h). when the transmitted data is written to __________ the serial i/o2 register (address 0346 16 ), the s rdy2 output goes to h (or the s rdy2 output goes to l). when a transmit/receive operation is started and the transfer clock goes to l, the s rdy2 output __________ goes to l (or the s rdy2 output goes to h). (5) s rdy2 input signal the s rdy2 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. the s rdy2 input signal becomes valid only when the s rdy2 input and the s busy2 output are used. when the internal synchronous clock is selected, input a l level signal into the s rdy2 input (or a h __________ level signal into the s rdy2 input) in the initial status[serial i/o initialization bit (bit 4 of address 0342 16 ) __________ = 0 ]. when a h level signal is input into the s rdy2 input (or a l level signal is input into the s rdy2 input) for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the s clk2i (i = __________ 1, 2) output and a transmit/receive operation is started. when s rdy2 input is driven l (or s rdy2 input is driven h) during transmit/receive operation, the transfer clock being output from s clk2i (i = 1, 2) remains active until after the system finishes sending or receiving the designated number of bits, without stopping the transmit/receive operation immediately. the handshake unit of the 8-bit serial i/o is 8 bits, and that of the automatic transfer serial i/o is 8 bits. when the external synchronous clock is selected, the s rdy2 input becomes one of the triggers to ____________ output the s busy2 signal. to start a transmit/receive operation (s busy2 output: l, (or s busy2 output: __________ h)), input a h level signal into the s rdy2 input (or a l level signal into the s rdy2 input,) and also write transmit data into the serial i/o2 register (address 0346 16 ).
114 serial i/o2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 99. handshake operation at serial i/o2 mutual connecting (1) figure 100. handshake operation at serial i/o2 mutual connecting (2) a: b: s clk2i (i = 1, 2) s rdy2 s busy2 s busy2 s rdy2 s clk2i (i = 1, 2) a: b: write to serial i/o2 re g ister s clk2i (i = 1, 2) s rdy2 s busy2 internal synchronous clock selection external synchronous clock selection write to serial i/o2 register a: b: s clk2i (i= 1, 2) s rdy2 s busy2 s busy2 s rdy2 s clk2i (i= 1, 2) a: b: write to serial i/o2 re g ister s clk2i (i= 1, 2) s rdy2 s busy2 internal synchronous clock selection external synchronous clock selection write to serial i/o2 register
115 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock f ad (note 2) v cc = 5v f ad /divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) v cc = 3v divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) resolution 8-bit or 10-bit (selectable) absolute precision v cc = 5v ? without sample and hold function 3lsb ? with sample and hold function (8-bit resolution) 2lsb ? without sample and hold function (10-bit resolution) 3lsb v cc = 3v ? without sample and hold function (8-bit resolution)(note 3) 2lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8pins (an 0 to an 7 ) a-d conversion start condition ?software trigger a-d conversion starts when the a-d conversion start flag changes to 1 conversion speed per pin ?without sample and hold function 8-bit resolution: 49 f ad cycles, 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles, 10-bit resolution: 33 f ad cycles note 1: does not depend on use of sample and hold function. note 2: without sample and hold function, set the f ad frequency to 250khz min. with the sample and hold function, set the f ad frequency to 1mhz min. note 3: only mask rom version. a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p10 0 to p10 7 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table 30 shows the performance of the a-d converter. figure 101 shows the block diagram of the a-d converter, and figures 102 and 103 show the a-d converter-related registers. table 30. performance of a-d converter
116 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 101. block diagram of a-d converter 1 / 2 a d 1 / 2 f a d a - d c o n v e r s i o n r a t e s e l e c t i o n ( 0 3 c 1 1 6 , 0 3 c 0 1 6 ) ( 0 3 c 3 1 6 , 0 3 c 2 1 6 ) ( 0 3 c 5 1 6 , 0 3 c 4 1 6 ) ( 0 3 c 7 1 6 , 0 3 c 6 1 6 ) ( 0 3 c 9 1 6 , 0 3 c 8 1 6 ) ( 0 3 c b 1 6 , 0 3 c a 1 6 ) ( 0 3 c d 1 6 , 0 3 c c 1 6 ) ( 0 3 c f 1 6 , 0 3 c e 1 6 ) c k s 1 = 1 c k s 0 = 0 a - d r e g i s t e r 0 ( 1 6 ) a - d r e g i s t e r 1 ( 1 6 ) a - d r e g i s t e r 2 ( 1 6 ) a - d r e g i s t e r 3 ( 1 6 ) a - d r e g i s t e r 4 ( 1 6 ) a - d r e g i s t e r 5 ( 1 6 ) a - d r e g i s t e r 6 ( 1 6 ) a - d r e g i s t e r 7 ( 1 6 ) r e s i s t o r l a d d e r s u c c e s s i v e c o n v e r s i o n r e g i s t e r a n 0 a n 1 a n 2 a n 3 a n 5 a n 6 a n 7 a - d c o n t r o l r e g i s t e r 0 ( a d d r e s s 0 3 d 6 1 6 ) a - d c o n t r o l r e g i s t e r 1 ( a d d r e s s 0 3 d 7 1 6 ) v r e f v i n v c u t = 0 d a t a b u s h i g h - o r d e r d a t a b u s l o w - o r d e r v r e f a v s s a n 4 v c u t = 1 c k s 0 = 1 c k s 1 = 0 c h 2 , c h 1 , c h 0 = 0 0 0 c h 2 , c h 1 , c h 0 = 0 0 1 c h 2 , c h 1 , c h 0 = 0 1 0 c h 2 , c h 1 , c h 0 = 0 1 1 c h 2 , c h 1 , c h 0 = 1 0 0 c h 2 , c h 1 , c h 0 = 1 0 1 c h 2 , c h 1 , c h 0 = 1 1 0 c h 2 , c h 1 , c h 0 = 1 1 1 d e c o d e r c o m p a r a t o r a d d r e s s e s
117 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 102. a-d converter-related registers (1) a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected ch0 ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 md0 md1 must always be ?? adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected must always be ?? w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 0 0 0
118 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 103. a-d converter-related registers (2) eight low-order bits of a-d conversion result a-d control register 2 (note) symbol address when reset adcon2 03d4 16 xxxxxxx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 without sample and hold 1 with sample and hold smp nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? a-d register i symbol address when reset adi (i=0 to 7) 03c0 16 to 03cf 16 indeterminate function w r (b15) b7 b7 b0 b0 (b8) ?during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? ?during 8-bit mode when read, the content is indeterminate note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate.
119 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conversion. table 31 shows the specifications of one-shot mode. figure 104 shows the a-d control register in one-shot mode. table 31. one-shot mode specifications item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ?end of a-d conversion (a-d conversion start flag changes to 0) ?writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin figure 104. a-d conversion register in one-shot mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 r bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0: f ad /4 is selected 1: f ad /2 is selected cks0 w 0 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected w r invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected b2 b1 b0 0 0 : one-shot mode b4 b3 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. must always be ?? must always be ?? 0 0 0
120 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. table 32 shows the specifications of repeat mode. figure 105 shows the a-d control register in repeat mode. table 32. repeat mode specifications item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion star condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin figure 105. a-d conversion register in repeat mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r 01 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected b2 b1 b0 0 1 : repeat mode b4 b3 note: if the a-d control register is rewritten during a-d conversion, the conversin result is indeterminate. a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 1 : vref connected w r invalid in repeat mode 0 1 frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note: if the a-d control register is rewritten during a-d conversion, the conversn result is indeterminate. 0 0 0 must always be ?? must always be ??
121 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (3) single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 33 shows the specifications of single sweep mode. figure 106 shows the a-d control register in single sweep mode. table 33. single sweep mode specifications item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ?end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ?writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin figure 106. a-d conversion register in single sweep mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 0 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 10 invalid in single sweep mode 0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 must always be ?? must always be ?? 0 0 0
122 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 34 shows the specifications of repeat sweep mode 0. figure 107 shows the a-d control register in repeat sweep mode 0. table 34. repeat sweep mode 0 specifications item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) figure 107. a-d conversion register in repeat sweep mode 0 a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 1 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 1 invalid in repeat sweep mode 0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 must always be ?? must always be ?? 0 0 0
123 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected -> an 0 -> an 1 -> an 0 -> an 2 -> an 0 -> an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin emphasis on the pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to an 3 (4 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table 35 shows the specifications of repeat sweep mode 1. figure 108 shows the a-d control register in repeat sweep mode 1. table 35. repeat sweep mode 1 specifications figure 108. a-d conversion register in repeat sweep mode 1 a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 1 : repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 1 invalid in repeat sweep mode 0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pins) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 1 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 must always be ?? must always be ?? 0 0 0
124 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (a) sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, 28 f ad cycles are achieved with 8-bit resolution and 33 f ad cycles with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used.
125 d-a converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 36 lists the performance of the d-a converter. figure 109 shows the block diagram of the d-a converter. figure 110 shows the d-a control register. figure 111 shows the d-a converter equivalent circuit. table 36. performance of d-a converter item performance conversion method r-2r method resolution 8 bits analog output pin 2 channels aaaaaaa aaaaaaa p9 7 /da 0 /clk out /dim out aaaaaa p9 6 /da 1 /sclk 22 data bus low-order bits d-a register0 (8) r-2r resistor ladder d-a0 output enable bit d-a register1 (8) r-2r resistor ladder d-a1 output enable bit (address 03d8 16 ) (address 03da 16 ) figure 109. block diagram of d-a converter
126 d-a converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 110. d-a control register d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? d-a register symbol address when reset dai (i = 0,1) 03d8 16 , 03da 16 indeterminate w r b7 b0 function r w output value of d-a conversion figure 111. d-a converter equivalent circuit v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r da0 msb lsb d-a0 output enable bit "0" "1" d-a0 register0 note 1: the above diagram shows an instance in which the d-a register is assigned 2a 16 . note 2: the same circuit as this is also used for d-a1. note 3: to reduce the current consumption when the d-a converter is not used, set the d-a output enable bit to 0 and set the d- a register to 00 16 so that no current flows in the resistors rs and 2rs.
127 crc calculation circuit m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcom- puter uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is com- pleted in two machine cycles. figure 112 shows the block diagram of the crc circuit. figure 113 shows the crc-related registers. figure 114 shows the calculation example using the crc calculation circuit figure 113. crc-related registers figure 112. block diagram of crc circuit aaaaaaaaaa aaaaaaaaaa crc code generating circt x 16 + x 12 + x 5 + 1 eight low-order bits aaaaa eight high-order bits data bus high-order bits data bus low-order bits aaaaaaaaaa aaaaaaaaaa aaaaaa aaaaaa crc data register (16) crc input register (8) (addresses 03bd 16 , 03bc 16 ) (address 03be 16 ) symbol address when reset crcd 03bd 16 , 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register w r crc calculation result output register function values that can be set 0000 16 to ffff 16 symbo address when reset crcin 03be 16 indeterminate b7 b0 crc input register w r data input register function values that can be set 00 16 to ff 16
128 crc calculation circuit m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 114. calculation example using the crc calculation circuit b15 b0 (1) setting 0000 16 crc data register crcd [03bd 16 , 03bc 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [03be 16 ] 2 cycles after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [03be 16 ] after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m16c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1
129 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r programmable i/o ports there are 48 programmable i/o ports: p3, p4 and p7 to p10. each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p3 and p4 0 to p4 3 are high-breakdown-voltage, p-channel open drain outputs, and have no built-in pull- down resistance. figures 115, 116 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a con- verter), they function as outputs regardless of the contents of the direction registers. when pins are to be used as the outputs for the d-a converter, do not set the direction registers to output mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figure 117 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. (2) port registers figure 118 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure 119 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. note: p3, p4 0 to p4 3 have no built-in pull-up resistance, because of these pin's are high-breakdown- voltage, p-channel open drain outputs. exclusive high-breakdown-voltage output ports there are 40 exclusive output ports: p0 to p2, p5 and p6. all ports have structure of high-breakdown-voltage p-channel open drain output. exclusive output ports except p2 have built-in pull-down resistance. figure ua-1 shows the configuration of the exclusive high-breakdown-voltage output ports.
130 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 115. programmable i/o ports (1) p7 0 to p7 2 , p8 0 to p8 5 , p8 7 , p9 3 (inside dotted-line included) p8 6 (inside dotted-line not included) p3 0 to p3 7 , p4 0 to p4 3 p4 4 , p9 2 ,p9 4 data bus pull-up selection data bus data bus data bus pull-up selection output ? output ? input to respective peripheral functions direction register port latch port latch port latch direction register port latch direction register p0 0 to p0 7 , p1 0 to p1 7 , p5 0 to p5 7 , p6 0 to p6 7 , (inside dotted-line included) p2 0 to p2 7 (inside dotted-line not included) output v ee
131 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 116. programmable i/o ports (2) p4 5 to p4 7 , p7 3 to p7 7 p9 0 , p9 1 , p9 5 p9 6 (inside dotted-line included) p9 7 (inside dotted-line not included) data bus pull-up selection data bus direction register port latch pull-up selection analog output d-a output enabled direction register port latch output ? output ? p10 0 to p10 7 data bus pull-up selection direction register port latch analog input input to respective peripheral functions input to respective peripheral functions
132 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 117. direction register p o r t p i d i r e c t i o n r e g i s t e r s y m b o la d d r e s s w h e n r e s e t p d i ( i = 3 t o 1 0 , e x c e p t 5 , 6 )0 3 e 7 1 6 , 0 3 e a 1 6 , 0 3 e f 1 6 00 1 6 0 3 f 2 1 6 , 0 3 f 3 1 6 , 0 3 f 6 1 6 00 1 6 b i t n a m ef u n c t i o n b i t s y m b o lw r b 7b 6b 5b 4b 3b 2b 1b 0 p d i _ 0p o r t p i 0 d i r e c t i o n r e g i s t e r p d i _ 1p o r t p i 1 d i r e c t i o n r e g i s t e r p d i _ 2p o r t p i 2 d i r e c t i o n r e g i s t e r p d i _ 3p o r t p i 3 d i r e c t i o n r e g i s t e r p d i _ 4p o r t p i 4 d i r e c t i o n r e g i s t e r p d i _ 5p o r t p i 5 d i r e c t i o n r e g i s t e r p d i _ 6p o r t p i 6 d i r e c t i o n r e g i s t e r p d i _ 7p o r t p i 7 d i r e c t i o n r e g i s t e r 0 : i n p u t m o d e ( f u n c t i o n s a s a n i n p u t p o r t ) 1 : o u t p u t m o d e ( f u n c t i o n s a s a n o u t p u t p o r t ) ( i = 3 t o 1 0 e x c e p t 5 , 6 ) port pi register symbol addres when reset pi (i = 0 to 10) 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 indeterminate 03e9 16 , 03ec 16 , 03ed 16 , 03f0 16 , 03f1 16 , 03f4 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data (i = 0 to 10) figure 118. port register
133 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 119. pull-up control register pull-up control register 0 symbol address when rese t pur0 03fd 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu01 p4 4 to p4 7 pull-up pu06 p7 0 to p7 3 pull-up pu07 p7 4 to p7 7 pull-up pull-up control register 1 symbol address when rese t pur1 03fe 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p8 0 to p8 3 pull-up pu11 p8 4 to p8 7 pull-up pu12 p9 0 to p9 3 pull-up pu13 p9 4 to p9 7 pull-up pu14 p10 0 to p10 3 pull-up pu15 p10 4 to p10 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate.
134 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 37. example connection of unused pins figure 120. example connection of unused pins p i n n a m ec o n n e c t i o n p o r t s p 3 , p 4 , p 7 t o p 1 0 s p e c i f y o u t p u t m o d e , a n d l e a v e t h e s e p i n s o p e n ; o r s p e c i f y i n p u t m o d e , a n d c o n n e c t t o v s s v i a r e s i s t o r ( p u l l - d o w n ) note 1: with external clock input to x in pin. note 2: connect a bypass capacitor. x o u t ( n o t e 1 ) , v e e a v s s , v r e f a v c c o p e n c o n n e c t t o v c c ( n o t e 2 ) c o n n e c t t o v s s ( n o t e 2 ) p o r t s p 0 t o p 2 , p 5 , p 6 le a v e t h e s e p i n s o p e n c n v s s c o n n e c t t o v s s v i a r e s i s t o r p o r t p 3 , p 4 , p 7 t o p 1 0 ( i n p u t m o d e ) ( o u t p u t m o d e ) p o r t p 0 t o p 2 , p 5 , p 6 ( o u t p u t m o d e ) x ou t a v c c ( n o t e 1 ) c nv s s a v s s ( n o t e 1 ) v r e f ( n o t e 1 ) m i c r o c o m p u t e r v cc v s s open open open v e e open n o t e 1 : c o n n e c t a b y p a s s c a p a c i t o r .
135 pull-down m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r power dissipation calculating method (fixed number depending on microcomputer? standard) ?v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ?resistor value = 68 k (min.) ?power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v x 38 ma = 190 mw ( fixed number depending on use condition) ?apply voltage to v ee pin: vcc ?50 v ?timing number a; digit number b; segment number c ?ratio of toff time corresponding tdisp time: 1/16 ?turn on segment number during repeat cycle: d ?all segment number during repeat cycle: e (= a x c) ?total number of built-in resistor: for digit; f, for segment; g ?digit pin current value h (ma) ?segment pin current value i (ma) (1) digit pin power dissipation {h x b x (1?off / tdisp) x voltage} / a (2) segment pin power dissipation {i x d x (1?off / tdisp) x voltage} / a (3) pull-down resistor power dissipation (digit) {power dissipation per 1 digit x (b x f / b) x (1?off / tdisp) } / a (4) pull-down resistor power dissipation (segment) {power dissipation per 1 segment x (d x g / c) x (1?off / tdisp) } / a (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190 mw (1) + (2)+ (3) + (4) + (5) = x mw
136 pull-down m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r power dissipation calculating example 1 fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 68 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v x 38 ma = 190 mw fixed number depending on use condition ? apply voltage to v ee pin: vcc C 50 v ? timing number 17; digit number 16; segment number 20 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 31 ? all segment number during repeat cycle: 340 (= 17 x 20) ? total number of built-in resistor: for digit; 16, for segment; 20 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation {18 x 16 x (1C1/16) x 2} / 17 = 31.77 mw (2) segment pin power dissipation {3 x 31 x (1C1/16) x 2} / 17 = 10.26 mw (3) pull-down resistor power dissipation (digit) (50 C 2) 2 /68 x (16 x 16/16) x (1 C 1/16) / 17 = 29.90 mw (4) pull-down resistor power dissipation (segment) (50 C 2) 2 /68 x (31 x 20/20) x (1 C 1/16) / 17 = 57.93 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190.00 mw (1) + (2)+ (3) + (4) + (5) = 319.86 mw dig0 dig1 dig2 dig3 dig13 dig14 dig15 timing number 12 3 1617 15 14 tscan repeat cycle figure 121. digit timing waveform (1)
137 pull-down m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r power dissipation calculating example 2(when 2 or more digit is turned on at same time) fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 68 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v x 38 ma = 190 mw fixed number depending on use condition ? apply voltage to v ee pin: vcc C 50 v ? timing number 11; digit number 12; segment number 24 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 114 ? all segment number during repeat cycle: 264 (= 11 x 24) ? total number of built-in resistor: for digit; 10, for segment; 22 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation {18 x 12 x (1C1 / 16) x 2} / 11 = 36.82 mw (2) segment pin power dissipation {3 x 114 x (1C1 / 16) x 2} / 11 = 58.30 mw (3) pull-down resistor power dissipation (digit) (50C 2) 2 / 68 x (12 x 10 / 12) x (1 C 1 / 16) / 11 = 28.88 mw (4) pull-down resistor power dissipation (segment) (50 C 2) 2 / 68 x (114 x 22 / 24) x (1 C 1 / 16) / 11 = 301.77 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190.00 mw (1) + (2)+ (3) + (4) + (5) = 615.77 mw (there is a limit of use temperature) dig0 dig1 dig2 dig3 dig7 dig8 dig9 timing number 12 34567 891011 dig4 dig5 dig6 tscan repeat cycle figure 122. digit timing waveform (2)
138 pull-down m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r power dissipation calculating example 3 (when 2 or more digit is turned on at same time, and used toff invalid function) fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 68 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v x 38 ma = 190 mw fixed number depending on use condition ? apply voltage to v ee pin: vcc C 50 v ? timing number 11; digit number 12; segment number 24 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 114 ( for toff invalid waveform;50) ? all segment number during repeat cycle: 264 (= 11 x 24) ? total number of built-in resistor: for digit; 10, for segment; 22 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation [{18 x 10 x (1C1/16) x 2} + {18 x 2 x 2}] / 11 = 37.23 mw (2) segment pin power dissipation [{3 x 64 x (1C1/16) x 2} + {3 x 50 x 2}] / 11 = 60.00 mw (3) pull-down resistor power dissipation (digit) [{(50C 2) 2 / 68 x (10 x 10 / 12) x (1 C 1 / 16)} + {(50C 2) 2 / 68 x (2 x 10 / 12) } ] /11 = 29.20 mw (4) pull-down resistor power dissipation (segment) [{(50C 2) 2 / 68 x (64 x 22 / 24) x (1 C 1 / 16)} + {(50C 2) 2 / 68 x (50 x 22 / 24) } ] / 11 = 310.59 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190.00 mw (1) + (2)+ (3) + (4) + (5) = 627.02 mw (there is a limit of use temperature) figure 123. digit timing waveform (3) dig0 dig1 dig2 dig3 dig7 dig8 dig9 timing number 12 34567 891011 dig4 dig5 dig6 tscan repeat cycle
139 electrical characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 38. absolute maximum ratings operating ambient temperature parameter unit v ref, x in input voltage reset , cnvss , analog supply voltage supply voltage output voltage v o - 0.3 to vcc+0.3 (note) p d storage temperature - 0.3 to 6.5 standard - 0.3 to 6.5 v v v condition v i avcc vcc t stg t opr symbol v -40 to 150 -20 to 85 p4 4 to p4 7, p7 0 to p7 7, p8 0 to p8 7, p9 0 to p9 7, p10 0 to p10 7, 2.7(note1) 5.5 typ. max. unit parameter vcc 5.0 supply voltage symbol min standard analog supply voltage vcc avcc v v 0 0 analog supply voltage supply voltage vss avss 0.8vcc v v v v 0.52vcc vcc vcc 0.16vcc 0 high input voltage low input voltage high input voltage p3 0 to p3 7, p4 0 to p4 3 v p3 0 to p3 7, p4 0 to p4 3 p7 0 to p7 7, p8 0 to p8 7, p9 0 to p9 7, p10 0 to p10 7, x in, reset , cnv ss v ih v ih v il pull-down supply voltage vcc - 50 to vcc+0.3v v v ee v i p3 0 to p3 7, p4 0 to p4 3 input voltage vcc - 50 to vcc+0.3 v p0 0 to p0 7, p1 0 to p1 7, p2 0 to p2 7, p3 0 to p3 7, p4 0 to p4 3, p5 0 to p5 7, output voltage v o p6 0 to p6 7 vcc - 50 to vcc+0.3 v v ee pull-down supply voltage vcc-48 vcc v v il low input voltage p7 0 to p7 7, p8 0 to p8 7, p9 0 to p9 7, p10 0 to p10 7, x in, reset , cnv ss 0 v 0.2vcc x out p4 4 to p4 7, p7 0 to p7 7, p8 0 to p8 7, p9 0 to p9 7, p10 0 to p10 7, -0.3 to vcc+0.3 power dissipation ta=-20 to 60 750 750-12 x (ta-60) ta=60 to 85 mw mw v ih p4 4 to p4 7 0.50vcc vcc v high input voltage v 0.16vcc 0 low input voltage p4 4 to p4 7 v il c c c c note 1: when writing to flash ,only cnvss is C0.3 to 13 (v) . note: v cc = 4.0v to 5.5v in flash memory version. table 39. recommended operating conditions (referenced to v cc = 2.7v to 5.5v at ta = C 20 to 85 o c unless otherwise specified) (note)
140 electrical characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 40. recommended operating conditions (referenced to v cc = 2.7v to 5.5v at ta = ?20 to 85 o c unless otherwise specified) (note 6) note 1: the total output current is the sum of all the currents through the applicable ports. the total average value measured over 100ms. the total peak current is the peak of all the currents. note 2: the peak output current is the peak current flowing in each port. note 3: the average output current in an average value measured over 100ms. note 4: when the oscillating frequency has a duty cycle of 50 %. note 5: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in ) / 3. note 6: v cc =4.0v to 5.5v in flash memory version. note 7: relationship between main clock oscillation frequency and supply voltage. aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaa a aa a a aa a a aa a a aa a a aa a aaaa 10.0 3.5 0.0 2.7 4.0 5.5 main clock input oscillation frequency (no wait) 5 x v cc -10.000mh z flash memory version operating maximum frequency [mh z ] supply voltage [v] (bclk: no division) i oh (avg) ma ma i oh (peak) -18 -40 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 f (x in ) mhz 10 f (xc in ) khz 50 32.768 vcc=4.0v to 5.5v vcc=2.7v to 4.0v mhz 0 0 5 x vcc-10 symbol parameter unit standard min typ. max. high peak output current (note 2) high average output current (note 3) main clock input oscillation frequency (note 4, 7) sub clock oscillation frequency (note 4, 5) p0 0 to p0 7 , p5 0 to p5 7 , p6 0 to p6 7 high total peak output current (note 1) i oh (peak) -240 ma p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 3 high total peak output current (note 1) i oh (peak) -240 ma p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 5 high total peak output current (note 1) i oh (peak) -80 ma p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 high total peak output current (note 1) i oh (peak) -80 ma p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 5 low total peak output current (note 1) i ol (peak) 80 ma p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 low total peak output current (note 1) i ol (peak) 80 ma p0 0 to p0 7 , p5 0 to p5 7 , p6 0 to p6 7 high total average output current (note 1) i oh (avg) -120 ma p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 3 high total average output current (note 1) i oh (avg) -120 ma p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 5 high total average output current (note 1) i oh (avg) -40 ma p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 high total average output current (note 1) i oh (avg) -40 ma p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 5 low total average output current (note 1) i ol (avg) 40 ma p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 low total average output current (note 1) i ol (avg) 40 ma ma i oh (peak) -10 p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 7 high peak output current (note 2) p9 0 to p9 7 , p10 0 to p10 7 ma i ol (peak) 10 p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 7 low peak output current (note 2) p9 0 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 i oh (avg) ma -5 high average output current (note 3) p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 7 p9 0 to p9 7 , p10 0 to p10 7 i ol (avg) ma 5 low average output current (note 3) p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 7 p9 0 to p9 7 , p10 0 to p10 7
141 electrical characteristics (v cc =5v) v cc =5v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 41. electrical characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c, f(x in ) =10mh z unless otherwise specified) x in , reset, cnvss s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e low input current i i l h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e standard typ. u n i t measuring condition v v v x o u t 3 . 0 3.0 v 2 . 0 a m i n .m a x . 3 . 5 p a r a m e t e r i oh = - 18ma i o h = - 1 m a i o h = - 5 m a i o h = - 0 . 5 m a i o l = 5 m a p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 v i = 0 v - 5.0 high power low power l o w o u t p u t v o l t a g e v o l h y s t e r e s i s h y s t e r e s i s high input current i i h v t + - v t - v t + - v t - v x o u t 2.0 2.0 0.2 0.8 v 0.2 1.8 v 5.0 a i o l = 1 m a i o l = 0 . 5 m a r e s e t p4 4 to p4 7 ,p7 0 to p7 7 ,p8 0 to p8 7 , v i =5v high power low power p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , clk 0 ,clk 1 ,srdy2 in ,sbsy2 in , i n t 0 t o i n t 5 , c t s 0 , c t s 1 , s i n 2 , s c l k 2 1 , s c l k 2 2 , r x d 0 , i ih p 3 0 t o p 3 7 , p 4 0 t o p 4 3 ( n o t e 1 ) v i =5v 5.0 a i i l p 3 0 t o p 3 7 , p 4 0 t o p 4 3 ( n o t e 1 ) v i =0v - 5 . 0 a r pullup pull-up resistance p4 4 to p4 7 ,p7 0 to p7 7 , p8 0 to p8 7 ,p9 0 to p9 7 , p10 0 to p10 7 p9 0 to p9 7 ,p10 0 to p10 7 , x in , reset, cnvss p9 0 to p9 7 ,p10 0 to p10 7 , i oh = - 5ma 4.5 30.0 50.0 1 6 7 . 0 k ? 3 . 0 r x d 1 r fxin feedback resistance x in 1.0 r pulld pull-down resistance p0 0 to p0 7 ,p1 0 to p1 7 , p5 0 to p5 7 ,p6 0 to p6 7 v ee =v cc - 48v,v ol =v cc output transistors off i leak output leak current p0 0 to p0 7 ,p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 4 ,p5 0 to p5 7 , p6 0 to p6 7 v e e = v c c - 4 8 v , v o l = v c c - 4 8 v o u t p u t t r a n s i s t o r s o f f 68 8 01 2 0 k ? ? ? high and x in pin to h level. note 3: this contains an electric current to flow into av cc pin.
142 electrical characteristics (v cc =5v) v cc =5v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 42. a-d conversion characteristics (referenced to v cc = av cc = v ref = 5v, vss = av ss = 0v at ta = 25 o c, f(x in ) = 10mh z unless otherwise specified) table 43. d-a conversion characteristics (referenced to v cc = 5v, v ss = av ss = 0v, v ref = 5v at ta = 25 o c, f(x in ) = 10mh z unless otherwise specified) m s standard min. typ. max. resolution absolute accuracy bits lsb v ref = v cc 3 10 symbol parameter measuring condition unit v ref = v cc = 5v r ladder t conv ladder resistance conversion time (10bit) reference voltage analog input voltage k w v v ia v ref v 0 2 10 v cc v ref 40 3.3 conversion time (8bit) 2.8 t conv t samp sampling time 0.3 v ref = v cc sample & hold function not available sample & hold function available(10bit) an 0 to an 7 input v ref =v cc = 5v lsb sample & hold function available(8bit) v ref = v cc = 5v 2 lsb m s m s 3 min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % k w ma i vref 1.0 1.5 8 3 symbol parameter measuring condition unit 20 10 4 m s ( note ) standard note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the vref is unconnected at the a-d control register, i vref is sent.
143 timing (v cc =5v) v cc =5v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 44. external clock input max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 15 100 40 40 15 switching characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 45. high-breakdown voltage p-channel open-drain output port symbol standard measuring condition max. typ. parameter unit min. t r(pch-strg) p-channel high-breakdown voltage output rising time (note 1) 55 ? ns t r(pch-weak) p-channel high-breakdown voltage output rising time (note 2) 1.8 c l =100pf v ee =v cc - 43v c l =100pf v ee =v cc - 43v note 1: when bit 7 of the fldc mode register (address 0350 16 ) is at ?? note 2: when bit 7 of the fldc mode re g ister ( address 0350 16 ) is at ?? v ee p0, p1, p2, p3, p4 0 to p4 3 , p5, p6 p-channel high- breakdown voltage output port (note) note: ports p2, p3, and p4 0 to p4 3 need external resistors. c l figure 124. circuit for measuring output switching characteristics
144 timing (v cc =5v) v cc =5v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 46. timer a input (counter input in event counter mode) table 47. timer a input (gating input in timer mode) table 48. timer a input (external trigger input in one-shot timer mode) table 49. timer a input (external trigger input in pulse width modulation mode) table 50. timer a input (up/down input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns unit standard max. min. ns ns ns unit ns ns tai in input high pulse width t w(tah) parameter symbol tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width symbol parameter t c(ta) tai in input cycle time tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 40 100 40 400 200 200 200 100 100 100 100 2000 1000 1000 400 400
145 timing (v cc =5v) v cc =5v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 52. timer b input (pulse period measurement mode) timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 51. timer b input (counter input in event counter mode) ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 250 250 200 100 100 0 30 90 80 ? ns ns ns standard max. min. serial i/o clock input cycle time serial i/o clock input high pulse width serial i/o clock input low pulse width t c(sclk) t wh(sclk) t wl(sclk) parameter symbol unit t su(sclk-sin) serial i/o input setup time t h(sclk-sin) serial i/o input hold time 0.95 400 200 200 ns 400 table 53. timer b input (pulse width measurement mode) table 54. serial i/o _______ table 55. external interrupt inti inputs table 56. automatic transfer serial i/o
146 timing (v cc =5v) v cc =5v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r t su(d-c) tai in input tai out input during event counter mode tbi in input clk i txd i rxd i t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) t h(t in -up) t su(up-t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) s out s in s clk 0.2v cc t d(sclk-sout) 0.2v cc 0.8v cc 0.8v cc t su(sin-sclk) t h(sclk-sin) t v(sclk-sout) t wl(sclk) t wh(sclk) tf (sclk) t c(sclk) t r
147 electrical characteristics(v cc =3v, only mask rom version) v cc =3v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 57. electrical characteristics (referenced to v cc = 3v, v ss = 0v at ta = 25 o c, f(x in ) =5mh z unless otherwise specified) x i n , r e s e t , c n v s s s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e low input current i i l h i g h o u t p u t v o l t a g e high output voltage s t a n d a r d t y p . unit measuring condition v v v x o u t 2.5 2 . 5 v 0.5 a m i n .max. 1.5 p a r a m e t e r i o h = - 1 8 m a i o h = - 0 . 1 m a i o h = - 1 m a i o h = - 5 0 a i o l = 1 m a p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p3 0 to p3 7 ,p4 0 to p4 3 ,p5 0 to p5 7 , p 6 0 t o p 6 7 v i = 0 v - 4 . 0 high power low power l o w o u t p u t v o l t a g e v o l h y s t e r e s i s h y s t e r e s i s high input current i i h v t + - v t - v t + - v t - v x o u t 0.5 0 . 5 0.2 0 . 8v 0 . 21 . 8v 4 . 0 a i o l = 0 . 1 m a i o l = 5 0 a reset p4 4 to p4 7 ,p7 0 to p7 7 ,p8 0 to p8 7 , v i =3v h i g h p o w e r low power p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 p4 4 to p4 7 ,p7 0 to p7 7 ,p8 0 to p8 7 , p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p9 0 to p9 7 ,p10 0 to p10 7 t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , clk 0 ,clk 1 ,srdy2 in ,sbsy2 in , i n t 0 t o i n t 5 , c t s 0 , c t s 1 , s i n 2 , s c l k 2 1 , s c l k 2 2 i i h p 3 0 t o p 3 7 , p 4 0 t o p 4 3 ( n o t e 1 ) v i = 3 v 4 . 0 a i il p 3 0 t o p 3 7 , p 4 0 t o p 4 3 ( n o t e 1 ) v i =0v - 4 . 0 a r p u l l u p p u l l - u p r e s i s t a n c e p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 p9 0 to p9 7 ,p10 0 to p10 7 , x i n , r e s e t , c n v s s p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , i o h = - 5 m a 2 . 5 6 6 . 0 120.0 5 0 0 . 0 k ? 2.5 r t s 0 , r t s 1 r fxin feedback resistance x in 3.0 r p u l l d p u l l - d o w n r e s i s t a n c e p0 0 to p0 7 ,p1 0 to p1 7 , p5 0 to p5 7 ,p6 0 to p6 7 v ee =v cc - 48v,v ol =v cc output transistors off i l e a k output leak current p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 4 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 v ee =v cc - 48v,v ol =v cc - 48v output transistors off 68 80 120 k ? ? ?
148 electrical characteristics(v cc =3v, only mask rom version) v cc =3v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 58. a-d conversion characteristics (referenced to v cc = av cc = v ref = 3v, vss = av ss = 0v at ta = 25 o c, f(x in ) = 5mh z unless otherwise specified) table 59. d-a conversion characteristics (referenced to v cc = 3v, v ss = av ss = 0v, v ref = 3v at ta = 25 o c, f(x in ) = 5mh z unless otherwise specified) r ladder ladder resistance reference voltage analog input voltage v v ia v ref v 0 2.7 10 v cc v ref 40 conversion time (8bit) 14.0 t conv v ref = v cc standard min. typ. max resolution absolute accuracy bits lsb v ref = v cc 2 10 symbol parameter measuring condition unit v ref = v cc = 3v, f ad = f(x in )/2 sample & hold function not available (8 bit) k w m s standard min. typ. max t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % ma i vref 1.0 1.0 8 3 symbol parameter measuring condition unit 20 10 4 (note) k w m s note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the vref is unconnected at the a-d control register, i vref is sent.
149 timing(v cc =3v, only mask rom version) v cc =3v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table 60. external clock input ns ns ns ns ns t c t w(h ) t w(l) t r t f max. min. parameter symbol unit standard external clock rise time external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time 200 85 85 18 18
150 timing(v cc =3v, only mask rom version) v cc =3v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table 61. timer a input (counter input in event counter mode) table 62. timer a input (gating input in timer mode) table 63. timer a input (external trigger input in one-shot timer mode) table 64. timer a input (external trigger input in pulse width modulation mode) table 65. timer a input (up/down input in event counter mode) standard max. min. unit parameter symbol ns t w(tal) tai in input low pulse width 60 ns t c(ta) tai in input cycle time 150 ns t w(tah) tai in input high pulse width 60 standard max. min. unit parameter symbol ns t c(ta) tai in input cycle time 600 ns t w(tah) tai in input high pulse width 300 ns t w(tal) tai in input low pulse width 300 standard max. min. unit parameter symbol ns t c(ta) tai in input cycle time 300 ns t w(tah) tai in input high pulse width 150 ns t w(tal) tai in input low pulse width 150 standard max. min. unit parameter symbol ns t w(tah) tai in input high pulse width 150 ns t w(tal) tai in input low pulse width 150 standard max. min. unit parameter symbol ns t c(up) tai out input cycle time 3000 ns t w(uph) tai out input high pulse width 1500 ns t w(upl) tai out input low pulse width 1500 ns t su(up-t in ) tai out input setup time 600 ns t h(t in- up) tai out input hold time 600
151 timing(v cc =3v, only mask rom version) v cc =3v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 67. timer b input (pulse period measurement mode) timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table 66. timer b input (counter input in event counter mode) table 68. timer b input (pulse width measurement mode) table 69. serial i/o _______ table 70. external interrupt inti inputs table 71. automatic transfer serial i/o standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time (counted on one edge) 150 ns t w(tbh) tbi in input high pulse width (counted on one edge) 60 ns t w(tbl) tbi in input low pulse width (counted on one edge) 60 t w(tbh) ns tbi in input high pulse width (counted on both edges) 160 t w(tbl) ns tbi in input low pulse width (counted on both edges) 160 t c(tb) ns tbi in input cycle time (counted on both edges) 300 standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time 600 ns t w(tbh) tbi in input high pulse width 300 t w(tbl) ns tbi in input low pulse width 300 standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time 600 ns t w(tbh) tbi in input high pulse width 300 t w(tbl) ns tbi in input low pulse width 300 standard max. min. parameter symbol unit ns t w(inh) inti input high pulse width 380 ns t w(inl) inti input low pulse width 380 standard max. min. parameter symbol unit ns t c(ck) clki input cycle time 300 ns t w(ckh) clki input high pulse width 150 ns t w(ckl) clki input low pulse width 150 t h(c-q) ns txdi hold time 0 t su(d-c) ns rxdi input setup time 50 t h(c-d) ns rxdi input hold time 90 t d(c-q) ns txdi output delay time 160 s ns ns ns standard max. min. serial i/o clock input cycle time serial i/o clock input high pulse width serial i/o clock input low pulse width t c(sclk) t wh(sclk) t wl(sclk) parameter symbol unit t su(sclk-sin) serial i/o input setup time t h(sclk-sin) serial i/o input hold time 2.0 ns 1000 1000 400 400
152 timing(v cc =3v, only mask rom version) v cc =3v m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r t su(d-c) tai in input tai out input during event counter mode tbi in input clk i txd i rxd i t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) t h(t in -up) t su(up-t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) s out s in s clk 0.2v cc t d(sclk-sout) 0.2v cc 0.8v cc 0.8v cc t su(sin-sclk) t h(sclk-sin) t v(sclk-sout) t wl(sclk) t wh(sclk) tf (sclk) t c(sclk) t r
153 description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r item power supply voltage program/erase voltage flash memory operation mode erase block division program method erase method program/erase control method number of commands program/erase count rom code protect performance 4.0v to 5.5 v (f(x in )=10mhz) v pp =12v 5% (f(x in )=10mhz) three modes (parallel i/o, standard serial i/o, cpu rewrite) see figure 1.aa.3. one division (3.5 k bytes) (note) in units of byte collective erase / block erase program/erase control by software command 6 commands 100 times standard serial i/o mode is supported. note: the boot rom area contains a standard serial i/o mode control program which is stored in it when shipped from the factory. this area can be erased and programmed in only parallel i/o mode. user rom area boot rom area v cc =5v 10% (f(x in )=10mhz) table 72. outline performance of the M30218 group (flash memory version) outline performance table 72 shows the outline performance of the M30218 group (flash memory version).
154 description m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r flash memory the M30218 group (flash memory version) contains the nor type of flash memory that requires a high- voltage v pp power supply for program/erase operations, in addition to the v cc power supply for device operation. for this flash memory, three flash memory modes are available in which to read, program, and erase: parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and a cpu rewrite mode in which the flash memory can be manipulated by the central pro- cessing unit (cpu). each mode is detailed in the pages to follow. in addition to the ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the user? application system. this boot rom area can be rewritten in only parallel i/o mode. figure 125. block diagram of flash memory version sfr ram sfr ram s f r r a m user rom area 0 0 0 0 0 1 6 0 0 4 0 0 1 6 yyyyy 16 d f 0 0 0 1 6 xxxxx 16 f f f f f 1 6 microcomputer mode parallel i/o mode cpu rewrite mode standard serial i/o mode boot rom area (3.5k bytes) u s e r r o m a r e a user rom area boot rom area (3.5k bytes) d f d f f 1 6 e0000 16 e8000 16 f0000 16 f8000 16 fffff 16 b l o c k 0 b l o c k 1 b l o c k 2 block 3 t y p e n o . xxxxx 16 yyyyy 16 M30218fc e0000 16 033ff 16 c o l l e c t i v e e r a s a b l e / p r o g r a m m a b l e a r e a collective erasable/ programmable area collective erasable/ programmable area n o t e 1 : i n c p u r e w r i t e a n d s t a n d a r d s e r i a l i / o m o d e s , t h e u s e r r o m i s t h e o n l y e r a s a b l e / p r o g r a m m a b l e a r e a . n o t e 2 : i n p a r a l l e l i / o m o d e , t h e a r e a t o b e e r a s e d / p r o g r a m m e d c a n b e s e l e c t e d b y t h e a d d r e s s a 1 7 i n p u t . t h e u s e r r o m a r e a i s s e l e c t e d w h e n t h i s a d d r e s s i n p u t i s h i g h a n d t h e b o o t r o m a r e a i s s e l e c t e d w h e n t h i s a d d r e s s i n p u t i s l o w .
155 cpu rewrite mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r cpu rewrite mode in cpu rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu rewrite mode, the flash memory can be operated on by reading or writing to the flash memory control register and flash command register. figure 126, figure 127 show the flash memory control register, and flash command register respectively. also, in cpu rewrite mode, the cnv ss pin is used as the v pp power supply pin. apply the power supply voltage, v pp h, from an external source to this pin. in cpu rewrite mode, only the user rom area shown in figure 128 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block commands are issued for only the user rom area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control program must be transferred to internal ram before it can be executed. flash memory control register 0 symbol address when reset fcon0 03b4 16 00100000 2 w r b7 b6 b5 b4 b3 b2 b1 b0 cpu rewrite mode select bit fcon00 bit symbol bit name function rw 0: cpu rewrite mode is invalid 1: cpu rewrite mode is valid this bit can not write. the value, if read, turns out to be indeterminate. reserved bit cpu rewrite mode monitor flag 0: cpu rewrite mode is invalid 1: cpu rewrite mode is valid must always be set to "0". fcon02 reserved bit 0 000: block 3 program/erase 001: block 2 program/erase 010: block 1 program/erase 011: block 0 program/erase 110: block 0 to 3 erase 111: inhibit 0 must always be set to "0". reserved bit flash memory control register 1 symbol address when reset fcon1 03b5 16 xxxxxx00 2 w r b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function rw 0 0 reserved bit nothing is assigned. in an attempt to write these bits, write "0". the value, if read, turns out to be indeterminate. must always be set to "0". fcon04 fcon05 fcon06 b6b5b4 erase / program area select bit flash command register symbol address when reset fcmd 03b6 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 writing of software command ?ead command "00 16 " ?rogram command "40 16 " ?rogram verify command "c0 16 " ?rase command "20 16 " + "20 16 " erase verify command "a0 16 " reset command "ff 16 " + "ff 6 " function rw a figure 126. flash memory control register figure 127. flash command register
156 cpu rewrite mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure 125 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low (v ss ). in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p5 2 pin high (v cc ), the cnv ss pin high(v pph ), the cpu starts operating using the control program in the boot rom area. this mode is called the boot mode. the control program in the boot rom area can also be used to rewrite the user rom area. cpu rewrite mode operation procedure the internal flash memory can be operated on to program, read, verify, or erase it while being placed on- board by writing commands from the cpu to the flash memory control register (addresses 03b4 16 , 03b5 16 ) and flash command register (address 03b6 16 ). note that when in cpu rewrite mode, the boot rom area cannot be accessed for program, read, verify, or erase operations. before this can be accom- plished, a cpu write control program must be written into the boot rom area in parallel input/output mode. the following shows a cpu rewrite mode operation procedure. (1) apply v pp h to the cnv ss /v pp pin and v cc to the port p4 6 pin for reset release. or the user can jump from the user rom area to the boot rom area using the jmp instruction and execute the cpu write control program. in this case, set the cpu write mode select bit of the flash memory control register to 1 before applying v pp h to the cnv ss /v pp pin. (2) after transferring the cpu write control program from the boot rom area to the internal ram, jump to this control program in ram. (the operations described below are controlled by this program.) (3) set the cpu rewrite mode select bit to 1. (4) read the cpu rewrite mode monitor flag to see that the cpu rewrite mode is enabled. (5) execute operation on the flash memory by writing software commands to the flash command regis- ter. note 1: in addition to the above, various other operations need to be performed, such as for entering the data to be written to flash memory from an external source (e.g., serial i/o), initializing the ports, and writing to the watchdog timer. (1) apply v ss to the cnv ss /v pp pin. (2) set the cpu rewrite mode select bit to 0.
157 cpu rewrite mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed during erase/program mode, set bclk to one of the following frequencies by changing the divide ratio: 5 mhz or less when wait bit (bit 7 at address 0005 16 ) = 0 (without internal access wait state) 10 mhz or less when wait bit (bit 7 at address 0005 16 ) = 1 (with internal access wait state)(note 1) (2) instructions inhibited against use the instructions listed below cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction (3) interrupts inhibited against use no interrupts can be used that look up the fixed vector table in the flash memory area. maskable interrupts may be used by setting the interrupt vector table in a location outside the flash memory area. note 1: internal access wait state can be set in cpu rewrite mode. in this time, the following function is only used. ? cpu, rom, ram, timer, uart, si/o2(non-automatic transfer), port in case of setting internal access wait state, refer to the following explain (software wait). software wait a software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16 ) (note 2). a software wait is inserted in the internal rom/ram area by setting the wait bit of the processor mode register 1. when set to 0, each bus cycle is executed in one bclk cycle. when set to 1, each bus cycle is executed in two bclk cycles. after the microcomputer has been reset, this bit defaults to 0. the sfr area is always accessed in two bclk cycles regardless of the setting of this control bit. table 73 shows the software wait and bus cycles. figure 128 shows example bus timing when using software waits. note 2: before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000a 16 ) to 1. area wait bit bus cycle 1 2 bclk cycles sfr internal rom/ram 0 1 bclk cycle invalid 2 bclk cycles table 73. software waits and bus cycles
158 cpu rewrite mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 128. typical bus timings using software wait output input address address bus cycle < internal bus (with wait) > bclk read signal write signal data bus address bus bclk read signal write signal address bus address address bus cycle < internal bus (no wait) > output data bus input
159 cpu rewrite mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r command program verify read program 03b6 16 first bus cycle second bus cycle 00 16 40 16 c0 16 write write write program address write read erase verify a0 16 write verify address verify data read erase 20 16 write 03b6 16 20 16 write verify address reset ff 16 write mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) 03b6 16 03b6 16 03b6 16 03b6 16 03b6 16 program data verify data ff 16 write 03b6 16 software commands table 74 lists the software commands available with the M30218 group (flash memory version). when cpu rewrite mode is enabled, write software commands to the flash command register to specify the operation to erase or program. the content of each software command is explained below. table 74. list of software commands (cpu rewrite mode) read command (00 16 ) the read mode is entered by writing the command code 00 16 to the flash command register in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (d 0 Cd 7 ), 8 bits at a time. the read mode is retained intact until another command is written. after reset and after the reset command is executed, the read mode is set. program command (40 16 ) the program mode is entered by writing the command code 40 16 to the flash command register in the first bus cycle. when the user execute an instruction to write byte data to the desired address (e.g., ste instruction) in the second bus cycle, the flash memory control circuit executes the program op- eration. the program operation requires approximately 20 m s. wait for 20 m s or more before the user go to the next processing. during program operation, the watchdog timer remains idle, with the value 7fff 16 set in it. note 1: the write operation is not completed immediately by writing a program command once. the user must always execute a program-verify command after each program command executed. and if verification fails, the user need to execute the program command repeatedly until the verification passes. see figure 129 for an example of a programming flowchart.
160 cpu rewrite mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r program-verify command (c0 16 ) the program-verify mode is entered by writing the command code c0 16 to the flash command register in the first bus cycle. when the user execute an instruction (e.g., lde instruction) to read byte data from the address to be verified (the previously programmed address) in the second bus cycle, the content that has actually been written to the address is read out from the memory. the cpu compares this read data with the data that it previously wrote to the address using the program command. if the compared data do not match, the user need to execute the program and program-verify operations one more time. erase command (20 16 + 20 16 ) the flash memory control circuit executes an erase operation by writing command code 20 16 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. the erase operation requires approximately 20 ms. wait for 20 ms or more before the user go to the next processing. before this erase command can be performed, all memory locations to be erased must have had data 00 16 written to by using the program and program-verify commands. during erase operation, the watchdog timer remains idle, with the value 7fff 16 set in it. note 1: the erase operation is not completed immediately by writing an erase command once. the user must always execute an erase-verify command after each erase command executed. and if verification fails, the user need to execute the erase command repeatedly until the verification passes. see figure 129 for an example of an erase flowchart. erase-verify command (a0 16 ) the erase-verify mode is entered by writing the command code a0 16 to the flash command register in the first bus cycle. when the user execute an instruction to read byte data from the address to be verified (e.g., lde instruction) in the second bus cycle, the content of the address is read out. the cpu must sequentially erase-verify memory contents one address at a time, over the entire area erased. if any address is encountered whose content is not ff 16 (not erased), the cpu must stop erase-verify at that point and execute erase and erase-verify operations one more time. note 1: if any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. in this case, however, the user does not need to write data 00 16 to memory before erasing.
161 cpu rewrite mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r start address = first location loop counter : x=0 write program command write : 40 16 duration = 20 s duration = 6 s x=25 ? verify ok ? pass fail fail pass yes pass no no fail write program data/ address loop counter : x=x+1 write program verify command last address ? next address ? write read command write read command verify ok ? write : program data write : c0 16 write : 00 16 write:20 16 duration = 6s x=1000 ? verify ok? pass fail fail pass yes pass no no fail duration = 20ms yes no start all bytes = "00 16 "? program all bytes = "00 16 " address = first address loop counter x=0 write erase command write erase command loop counter x=x+1 write erase verify command/address verify ok? last address? next address write read command write read command write:20 16 write:a0 16 write:00 16 read: expect value=ff 16 figure 129. program and erase execution flowchart in the cpu rewrite mode program erase reset command (ff 16 + ff 16 ) the reset command is used to stop the program command or the erase command in the middle of operation. after writing command code 40 16 or 20 16 twice to the flash command register, write command code ff 16 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. the program command or erase command is disabled, with the flash memory placed in read mode.
162 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r pin description v cc ,v ss apply 5v 10 % to vcc pin and 0 v to vss pin. cnv ss apply 12v 5 % to this pin. reset reset input pin. while reset is "l" level, a 20 cycle or longer clock must be input to xin pin. x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out av cc , av ss v ref connect av ss to vss and avcc to vcc, respectively. enter the reference voltage for ad from this pin. p0 0 to p0 7 output exclusive use pin. p1 0 to p1 7 output exclusive use pin. p2 0 to p2 7 output exclusive use pin. p3 0 to p3 7 input "h" or "l" level signal or open. p4 0 to p4 3 input "h" or "l" level signal or open. p4 4 serial data output pin. p4 5 p4 6 serial clock input pin. p4 7 p5 0 to p5 7 output exclusive use pin. name power input cnv ss reset input clock input clock output analog power supply input reference voltage input output port p0 output port p1 output port p2 input port p3 input port p4 txd output sclk input busy output output port p5 i/o i i i o i o o o i i i i o o rxd input serial data input pin. o busy signal output pin. p6 0 to p6 7 output exclusive use pin. p7 0 to p7 7 input "h" or "l" level signal or open. output port p6 input port p7 o i p8 0 to p8 7 input "h" or "l" level signal or open. input port p8 i p9 0 to p9 7 input "h" or "l" level signal or open. input port p9 i p10 0 to p10 7 input "h" or "l" level signal or open. input port p10 i pin functions (flash memory standard serial i/o mode)
163 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 130. pin connections for serial i/o mode (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 M30218fcfp p6 0 /fld0 p6 1 /fld1 p6 2 /fld2 p6 3 /fld3 p6 4 /fld4 p6 5 /fld5 p6 6 /fld6 p6 7 /fld7 p5 0 /fld8 v cc x in reset x out v ss cnv ss p8 6 /x cout p8 7 /x cin p9 0 /srdy2 p7 6 /ta3 in /ta1 out /clk1 p7 7 /ta4 in /ta2 out /cts1/rts1/clks1 p9 4 /s out 2 p9 5 /sclk21 p9 6 /da1/sclk22 p9 7 /da0/clk out /dim out p9 2 /sstb2 p9 3 /s in2 p7 3 /ta0 in /ta3 out p7 2 /tb2 in p9 1 /sbusy2 v ee p10 7 /an7 p10 6 /an6 p10 5 /an5 p10 3 /an3 p10 2 /an2 p10 4 /an4 p10 1 /an1 av ss p10 0 /an0 v ref av cc p5 1 /fld9 p5 2 /fld10 p5 3 /fld11 p5 4 /fld12 p5 5 /fld13 p5 6 /fld14 p5 7 /fld15 p0 0 /fld16 p0 1 /fld17 p0 2 /fld18 p0 3 /fld19 p0 4 /fld20 p0 5 /fld21 p0 6 /fld22 v ss p0 7 /fld23 v cc p1 0 /fld24 p1 1 /fld25 p1 2 /fld26 p1 3 /fld27 p1 4 /fld28 p1 5 /fld29 p1 6 /fld30 p1 7 /fld31 p2 0 /fld32 p2 1 /fld33 p2 2 /fld34 p2 3 /fld35 p2 4 /fld36 p2 5 /fld37 p2 6 /fld38 p2 7 /fld39 p3 0 /fld40 p3 1 /fld41 p3 2 /fld42 p3 3 /fld43 p3 4 /fld44 p3 5 /fld45 p3 6 /fld46 p3 7 /fld47 p4 0 /fld48 p4 1 /fld49 p4 2 /fld50 p4 3 /fld51 p4 4 /t x d0/fld52 p4 5 /r x d0/fld53 p4 6 /clk0/fld54 p47/cts0/rts0/fld55 p7 5 /ta2 in /ta0 out /r x d1 p7 4 /ta1 in /ta4 out /t x d1 p7 1 /tb1 in p7 0 /tb0 in p8 5 /int5 p8 4 /int4 p8 3 /int3 p8 2 /int2 p8 1 /int1 p8 0 /int0 vss vcc cnvss vss vcc cnvss vpph reset txd sclk rxd busy reset vss vcc mode setup method signal value v ss v cc connect oscillator circuit.
164 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r standard serial i/o mode the standard serial i/o mode serially inputs and outputs the software commands, addresses and data necessary for operating (read, program, erase, etc.) the internal flash memory. it uses a purpose-specific serial programmer. the standard serial i/o mode differs from the parallel i/o mode in that the cpu controls operations like rewriting (uses the cpu rewrite mode) in the flash memory or serial input for rewriting data. the standard serial i/o mode is started by clearing the reset with v pph at the cnvss pin. (for the normal microprocessor mode, set cnvss to l.) this control program is written in the boot rom area when shipped from mitsubishi electric. therefore, if the boot rom area is rewritten in the parallel i/o mode, the standard serial i/o mode cannot be used. figure 130 shows the pin connections for the standard serial i/o mode. serial data i/o uses three uart0 pins: clk 0 , rxd 0 , txd 0 , and rts 0 (busy). the clk 0 pin is the transfer clock input pin and it transfers the external transfer clock. the txd 0 pin outputs the cmos signal. the rts 0 (busy) pin outputs an l level when reception setup ends and an h level when the reception operation starts. transmission and reception data is transferred serially in 8-byte blocks. in the standard serial i/o mode, only the user rom area shown in figure 125 can be rewritten, the boot rom area cannot. the standard serial i/o mode has a 7-byte id code. when the flash memory is not blank and the id code does not match the content of the flash memory, the command sent from the programmer is not accepted. function overview (standard serial i/o mode) in the standard serial i/o mode, software commands, addresses and data are input and output between the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial i/o (uart0) . in reception, the software commands, addresses and program data are synchronized with the rise of the transfer clock input to the clk 0 pin and input into the flash memory via the rxd 0 pin. in transmission, the read data and status are synchronized with the fall of the transfer clock and output to the outside from the txd 0 pin. the txd 0 pin is cmos output. transmission is in 8-bit blocks and lsb first. when busy, either during transmission or reception, or while executing an erase operation or program, the rts 0 (busy) pin is h level. accordingly, do not start the next transmission until the rts 0 (busy) pin is l level. also, data in memory and the status register can be read after inputting a software command. it is pos- sible to check flash memory operating status or whether a program or erase operation ended success- fully or in error by reading the status register. software commands and the status register are explained here following.
165 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r software commands table 75 lists software commands. in the standard serial i/o mode, erase operations, programs and reading are controlled by transferring software commands via the rxd pin. software commands are explained here below. table 75. software commands (standard serial i/o mode) control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 bclock ease 4 erase all unlocked blocks 5 read status register 6 clear status register 7 read lockbit status 8 id check function 9 download function 10 version data output function 11 boot area output function note1: shading indicates transfer from flash memory microcomputer to serial programmer. all other data is transferred from the serial programmer to the flash memory microcomputer. note2: srd refers to status register data. srd1 refers to status register 1 data. note3: all commands can be accepted when the flash memory is totally blank. when id is not verificate not acceptable not acceptable not acceptable not acceptable acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable version data output to 9th byte data output to 259th byte data output to 259th byte data input to 259th byte to id7 data output data input id1 to required number of times version data output data output data output data input id size data input version data output data output data output data input d0 16 lock bit data output address (high) check- sum version data output data output address (high) address (high) address (high) srd1 output address (high) address (middle) size (high) version data output address (high) address (middle) address (middle) address (middle) d0 16 srd output address (middle) address (low) size (low) version data output address (middle) ff 16 41 16 20 16 a7 16 70 16 50 16 71 16 f5 16 fa 16 fb 16 fc 16 1st byte transfer
166 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) send the ff 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. data0 data255 clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 ff 16 srd output srd1 output clk0 rxd0 txd0 rts0(busy) 70 16 figure 131. timing for page read read status register command this command reads status information. when the 70 16 command code is sent in the 1st byte of the transmission, the contents of the status register (srd) specified in the 2nd byte of the transmission and the contents of status register 1 (srd1) specified in the 3rd byte of the transmission are read. figure 132. timing for reading the status register
167 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 133. timing for clearing the status register page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) send the 41 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respectively. (3) from the 4th byte onward, as write data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. when reception setup for the next 256 bytes ends, the rts 0 (busy) signal changes from the h to the l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. clk0 rxd0 txd0 rts0(busy) 50 16 clear status register command this command clears the bits (sr3Csr4) which are set when the status register operation ends in error. when the 50 16 command code is sent in the 1st byte of the transmission, the aforementioned bits are cleared. when the clear status register operation ends, the rts 0 (busy) signal changes from the h to the l level. clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 41 16 data0 data255 figure 134. timing for the page program
168 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r block erase command this command erases the data in the specified block. execute the block erase command as explained here following. (1) send the 20 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) send the verify command code d0 16 in the 4th byte of the transmission. with the verify com- mand code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . when block erasing ends, the rts0 (busy) signal changes from the h to the l level. after block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. figure 135.timing for block erasing a 8 to a 15 a 16 to a 23 20 16 d0 16 clk0 rxd0 txd0 rts0(busy)
169 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r read lock bit status command this command reads the lock bit status of the specified block. execute the read lock bit status com- mand as explained here following. (1) send the 71 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) the lock bit data of the specified block is output in the 4th byte of the transmission. write the highest address of the specified block for addresses a 8 to a 23 . the M30218 group (flash memory version) does not have the lock bit, so the read value is always 1 (block unlock). clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 71 16 dq6 figure 137. timing for reading lock bit status erase all unlocked blocks command this command erases the content of all blocks. execute the erase all unlocked blocks command as explained here following. (1) send the a7 16 command code in the 1st byte of the transmission. (2) send the verify command code d0 16 in the 2nd byte of the transmission. with the verify com- mand code, the erase operation will start and continue for all blocks in the flash memory. when block erasing ends, the rts 0 (busy) signal changes from the h to the l level. the result of the erase operation can be known by reading the status register. clk0 rxd0 txd0 rts0(busy) a7 16 d0 16 figure 136. timing for erasing all unlocked blocks
170 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) send the fa 16 command code in the 1st byte of the transmission. (2) send the program size in the 2nd and 3rd bytes of the transmission. (3) send the check sum in the 4th byte of the transmission. the check sum is added to all data sent in the 5th byte onward. (4) the program to execute is sent in the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. fa 16 program data program data data size (high) data size (low) check sum clk0 rxd0 txd0 rts0(busy) figure 138. timing for download
171 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) send the fb 16 command code in the 1st byte of the transmission. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure 139. timing for version information output boot area output command this command outputs the control program stored in the boot area in one page blocks (256 bytes). execute the boot area output command as explained here following. (1) send the fc 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. fb 16 'x' 'v' 'e' 'r' clk0 rxd0 txd0 rts0(busy) data0 data255 clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 fc 16 figure 140. timing for boot area output
172 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r id check this command checks the id code. execute the boot id check command as explained here following. (1) send the f5 16 command code in the 1st byte of the transmission. (2) send addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code in the 2nd, 3rd and 4th bytes of the transmission respectively. (3) send the number of data sets of the id code in the 5th byte. (4) the id code is sent in the 6th byte onward, starting with the 1st byte of the code. id size id1 id7 clk0 rxd0 txd0 rts0(busy) f5 16 df 16 ff 16 0f 16 figure 141. timing for the id check id code when the flash memory is not blank, the id code sent from the serial programmer and the id code written in the flash memory are compared to see if they match. if the codes do not match, the com- mand sent from the serial programmer is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , and 0ffff7 16 . write a program into the flash memory, which already has the id code set for these addresses. reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address figure 142. id code storage addresses
173 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table 76 gives the definition of each status register bit. after clearing the reset, the status register outputs 80 16 . table 76. status register (srd) status bit (sr7) the status bit indicates the operating status of the flash memory. when power is turned on, 1 (ready) is set for it. the bit is set to 0 (busy) during an auto write or auto erase operation, but it is set back to 1 when the operation ends. erase bit (sr5) the erase bit reports the operating status of the auto erase operation. if an erase error occurs, it is set to 1. when the erase status is cleared, it is set to 0. program bit (sr4) the program bit reports the operating status of the auto write operation. if a write error occurs, it is set to 1. when the program status is cleared, it is set to 0. srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) status name status bit reserved erase bit program bit reserved reserved reserved reserved definition "1" "0" ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - -
174 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r status register 1 (srd1) status register 1 indicates the status of serial communications, results from id checks and results from check sum comparisons. it can be read after the srd by writing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table 77 gives the definition of each status register 1 bit. 00 16 is output when power is turned on and the flag status is maintained even after the reset. table 77. status register 1 (srd1) boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the down- load function. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. srd1 bits sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) status name boot update completed bit reserved reserved checksum match bit id check completed bits data receive time out reserved definition "1" "0" update completed - - match 00 01 10 11 not update - - mismatch normal operation - not verified verification mismatch reserved verified time out -
175 appendix standard serial i/o mode m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r example circuit application for the standard serial i/o mode the below figure shows a circuit application for the standard serial i/o mode. control pins will vary ac- cording to programmer, therefore see the programmer manual for more information. rts0(busy) clk0 r x d0 t x d0 cnvss clock input rts output data input data output M30218 flash memory version (1) control pins and external circuitry will vary according to programmer. for more information, see the programmer manual. (2) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. v pp figure 143. example circuit application for the standard serial i/o mode
176 m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r qfp100-p-1420-0.65 1.58 weight(g) jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 5 20mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 x 0.13 b x m
chapter 2 peripheral functions usage
178 protect m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.1.2 protect operation the following explains the protect operation. figure 2.1.2 shows the set-up procedure. (1) setting 1 in the write-enable bit of system clock control registers 0 and 1 causes system clock control register 0 and system clock control register 1 to be in write-enabled state. (2) the contents of system clock control register 0 and that of system clock control register 1 are changed. (3) setting 0 in the write-enable bit of system control registers 0 and 1 causes system clock control register 0 and system control register 1 to be in write-inhibited state. (4) to change the contents of processor mode register 0 and that of processor mode register 1, follow the same steps as in dealing with system clock control registers. operation 2.1.1 overview 'protect' is a function that causes a value held in a register to be unchanged even when a program runs away. the following is an overview of the protect function: (1) registers affected by the protect function the registers affected by the protect function are: (a) system clock control registers 0, 1 (addresses 0006 16 and 0007 16 ) (b) processor mode registers 0, 1 (addresses 0004 16 and 0005 16 ) the values in registers (1) through (2) cannot be changed in write-protect state. to change values in the registers, put the individual registers in write-enabled state. (2) protect register figure 2.1.1 shows protect register. 2.1 protect figure 2.1.1. protect register p r o t e c t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p r c r0 0 0 a 1 6 x x x x x 0 0 0 2 b i t n a m e b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 0 : w r i t e - i n h i b i t e d 1 : w r i t e - e n a b l e d p r c 1 p r c 0 e n a b l e s w r i t i n g t o p r o c e s s o r m o d e r e g i s t e r s 0 a n d 1 ( a d d r e s s e s 0 0 0 4 1 6 a n d 0 0 0 5 1 6 ) f u n c t i o n 0 : w r i t e - i n h i b i t e d 1 : w r i t e - e n a b l e d e n a b l e s w r i t i n g t o s y s t e m c l o c k c o n t r o l r e g i s t e r s 0 a n d 1 ( a d d r e s s e s 0 0 0 6 1 6 a n d 0 0 0 7 1 6 ) w r n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e .
179 protect m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.1.2. set-up procedure for protect function (1) clearing the protect (set to write-enabled state) protect register [address 000a 16 ] prcr enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) 1 : write-enabled b7 b0 1 (3) setting the protect (set to write-inhibited state) protect register [address 000a 16 ] prcr enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) 0 : write-inhibited b7 b0 0 setting system clock control register i (i = 0, 1) (2)
180 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.2.1 overview the following is an overview for timer a, a 16-bit timer. (1) mode timer a operates in one of the four modes: (a) timer mode in this mode, the internal count source is counted. two functions can be selected: the pulse output function that reverses output from a port every time an overflow occurs, or the gate function which controls the count start/stop according to the input signal from a port. ? timer mode operation ......................................................................................................... ..... p186 ? timer mode, gate function operation ........................................................................................ p1 88 ? timer mode, pulse output function operation ........................................................................... p190 (b) event counter mode this mode counts the pulses from the outside and the number of underflows in other timers. the free-run type, in which nothing is reloaded from the reload register, can be selected when an under- flow occurs. the pulse output function can also be selected. please refer to the timer mode expla- nation for details, as the operation is identical. ? event counter mode operation ................................................................................................. p192 ? event counter mode, free run type operation ........................................................................... p194 furthermore, timer a has a 2-phase pulse signal processing function which generates an up count or down count in the event counter mode, depending on the phase of the two input signals. ? operation of the 2-phase pulse signal processing function in normal event counter mode ..... p196 ? operation of the 2-phase pulse signal processing function in 4-multiplication mode ............... p198 (c) one-shot timer mode in this mode, the timer is started by the trigger and stops when the timer goes to 0. the trigger can be selected from the following 3 types: an external input signal, an overflow of the timer, or a software trigger. the pulse output function can also be selected. please refer to the timer mode explanation for details, as the operation is identical. ? operation in one-shot timer mode effected by software ........................................................... p200 ? operation in one-shot timer mode effected by an external trigger ........................................... p202 (d) pulse width modulation (pwm) mode in this mode, the arbitrary pulses are successively output. either a 16-bit fixed-period pwm mode or 8-bit variable-period mode can be selected. the trigger for initiating output can also be selected. please refer to the one-shot timer mode explanation for details, as the operation is identical. ? 16-bit pwm mode operation .................................................................................................... . p204 ? 8-bit pwm mode operation ..................................................................................................... .. p206 2.2 timer a
181 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (2) count source the internal count source can be selected from f1, f 8 , f 32 , and f c32 . clocks f 1 , f 8 , and f 32 are derived by dividing the cpu's main clock by 1, 8, and 32 respectively. clock f c32 is derived by dividing the cpu's secondary clock by 32. (3) frequency division ratio in timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the frequency division ratio. in event counter mode, [the set value + 1] becomes the frequency division ratio when a down count is performed, or [ffff 16 - the set value + 1] becomes the frequency division ratio when an up count is performed. in one-shot timer mode, the value set in the timer register be- comes the frequency division ratio. the counter overflows (or underflows) when a count source equal to a frequency division ratio is input, and an interrupt occurs. for the pulse output function, the output from the port varies (the value in the port register does not vary). (4) reading the timer either in timer mode or in event counter mode, reading the timer register takes out the count at that moment. read it in 16-bit units. the data either in one-shot timer mode or in pulse width modulation mode is indeterminate. (5) writing to the timer to write to the timer register when a count is in progress, the value is written only to the reload register. when writing to the timer register when a count is stopped, the value is written both to the reload register and to the counter. write a value in 16-bit units. (6) relation between the input/output to/from the timer and the direction register with the output function of the timer, pulses are output regardless of the direction register of the relevant port. to input an external signal to the timer, set the direction register of the relevant port to input. (7) pins related to timer a (a) ta0 in , ta1 in , ta2 in , ta3 in , ta4 in input pins to timer a. (b) ta0 out , ta1 out , ta2 out , ta3 out , ta4 out output pins from timer a. they become input pins to timer a when event counter mode is active. (8) registers related to timer a figure 2.2.1 shows the memory map of timer a-related registers. figures 2.2.2 through 2.2.5 show timer a-related registers.
182 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.2. timer a-related registers (1) figure 2.2.1. memory map of timer a-related registers 0055 16 0056 16 0057 16 0058 16 0059 16 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0396 16 0397 16 0398 16 0399 16 039a 16 timer a0 (ta0) timer a1 (ta1) timer a2 (ta2) count start flag (tabsr) one-shot start flag (onsf) up-down flag (udf) timer a3 (ta3) timer a4 (ta4) trigger select register (trgsr) clock prescaler reset flag (cpsrf) timer a1 interrupt control register (ta1ic) timer a3 interrupt control register (ta3ic) timer a0 interrupt control register (ta0ic) timer a2 interrupt control register (ta2ic) timer a4 interrupt control register (ta4ic) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit aa aa a a aa aa a a aa aa a a aa a aa a aa a aa aa a a aa a
183 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.3. timer a-related registers (2) symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s symbol address when reset ta0 0387 16 ,0386 16 indeterminate ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta3 038d 16 ,038c 16 indeterminate ta4 038f 16 ,038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (note) w r ?timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set ?event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow ?one-shot timer mode 0000 16 to ffff 16 counts a one shot width ?pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator ?pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to fe 16 (both high-order and low-order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units.
184 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.4. timer a-related registers (3) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address when reset udf 0384 16 00 16 ta4p ta3p ta2p up/down flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to ? ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0382 16 00x00000 2 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be i ndeterminate. ta0tgl ta0tgh 0 0 : input on ta0 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note: set the corresponding port direction register to ?? when selecting the tai in (i = 0?) pin, tai out (i = 0?) pin which is assigned to the same pin cannot be used. w r 1 : timer start when read, the value is ?
185 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.5. timer a-related registers (4) symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? cpsr w r nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to ?? when selecting the tai in (i = 0?) pin, tai out (i = 0?) pin which is assigned to the same pin cannot be used.
186 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in timer mode, choose functions from those listed in table 2.2.1. operations of the circled items are described below. figure 2.2.6 shows the operation timing, and figure 2.2.7 shows the set-up procedure. operation (1) setting the count start flag to 1 causes the counter to perform a down count on the count source. (2) if an underflow occurs, the content of the reload register is reloaded, and the count continues. at this time, the timer ai interrupt request bit goes to 1. (3) setting the count start flag to 0 causes the counter to hold its value and to stop. 2.2.2 operation of timer a (timer mode) table 2.2.1. choosed functions figure 2.2.6. operation timing of timer mode ffff 16 n 0000 16 time start count again count start flag timer ai interrupt request bit ? ? counter content (hex) n = reload register content set to ?? by software ? ? set to ?? by software cleared to ?? by software cleared to ??when interrupt request is accepted, or cleared by software (1) start count (2) underflow (3) stop count item count source pulse output function gate function set-up o o o internal count source (f 1 / f 8 / f 32 / fc 32 ) no pulses output pulses output no gate function performs count only for the period in which the tai in pin is at ??level performs count only for the period in which the tai in pin is at ??level
187 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.7. set-up procedure of timer mode setting divide ratio can be set to 0000 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 start count setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0 setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) selecting timer mode and functions timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) selection of timer mode b7 b0 00 00 0 0 (must always be ??in timer mode) count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2s 976.56s 00 01 10 11 f 1 f 8 f 32 f c32 gate function select bit 0 0 : 0 1 : b4 b3 gate function not available (tai in pin is a normal port pin)
188 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.2.3 operation of timer a (timer mode, gate function selected) figure 2.2.8. operation timing of timer mode, gate function selected in timer mode, choose functions from those listed in table 2.2.2. operations of the circled items are described below. figure 2.2.8 shows the operation timing, and figure 2.2.9 shows the set-up procedure. table 2.2.2. choosed functions (1) when the count start flag is set to 1 and the tai in pin inputs at h level, the counter per- forms a down count on the count source. (2) when the tai in pin inputs at l level, the counter holds its value and stops. (3) if an underflow occurs, the content of the reload register is reloaded and the count continues. at this time, the timer ai interrupt request bit goes to 1. (4) setting the count start flag to 0 causes the counter to hold its value and to stop. ? make the pulse width of the signal input to the tai in pin not less than two cycles of the count source. operation note ffff 16 n 0000 16 time count start flag timer ai interrupt request bit ?? ?? counter content (hex) n = reload register content tai in pin input signal (2) stop count ?? ?? set to ??by software ?? ?? (4) stop count (1) start count cleared to ??when interrupt request is accepted, or cleared by software (3) underflow set to ??by software cleared to ??by software start count again. item count source pulse output function gate function set-up o o o internal count source(f 1 / f 8 / f 32 / fc 32 ) no pulses output pulses output no gate function performs count only for the period in which the tai in pin is at ??level performs count only for the period in which the tai in pin is at ??level
189 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.9. set-up procedure of timer mode, gate function selected setting divide ratio can be set to 0000 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) selecting timer mode and functions timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) gate function select bit 1 1 : timer counts only when ta iin pin is held ??(note) b4 b3 selection of timer mode b7 b0 00 00 0 (must always be ??in timer mode) count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note: set the corresponding port direction register to ?? 1 1 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2s 976.56s 00 01 10 11 f 1 f 8 f 32 f c32 setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0 setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 start count
190 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.10. operation timing of timer mode, pulse output function selected 2.2.4 operation of timer a (timer mode, pulse output function selected) in timer mode, choose functions from those listed in table 2.2.3. operations of the circled items are described below. figure 2.2.10 shows the operation timing, and figure 2.2.11 shows the set-up proce- dure. table 2.2.3. choosed functions (1) setting the count start flag to 1 causes the counter to perform a down count on the count source. (2) if an underflow occurs, the content of the reload register is reloaded and the count continues. at this time, the timer ai interrupt request bit goes to 1. also, the output polarity of the tai out pin reverses. (3) setting the count start flag to 0 causes the counter to hold its value and to stop. also, the tai out pin outputs an l level. operation ffff 16 n 0000 16 time count start flag timer ai interrupt request bit ? ? counter content (hex) n = reload register content pulse output from tai out pin ? ? ? ? set to ?? by software set to ?? by software cleared to ?? by software (3) stop count cleared to ??when interrupt request is accepted, or cleared by software (1) start count (2) underflow start count again item count source pulse output function gate function set-up o o o internal count source(f 1 / f 8 / f 32 / fc 32 ) no pulses output pulses output no gate function performs count only for the period in which the tai in pin is at ??level performs count only for the period in which the tai in pin is at ??level
191 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.11. set-up procedure of timer mode, pulse output function selected setting divide ratio can be set to 0000 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 start count setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0 pulse output function select bit 1 : pulse is output (note) (ta iout pin is a pulse output pin) selecting timer mode and functions timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) selection of timer mode b7 b0 00 01 0 0 (must always be ??in timer mode) count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note: the settings of the corresponding port register and port direction register are invalid. setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32 gate function select bit 0 0 : 0 1 : b4 b3 gate function not available (tai in pin is a normal port pin)
192 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.12. operation timing of event counter mode, reload type selected 2.2.5 operation of timer a (event counter mode, reload type selected) in event counter mode, choose functions from those listed in table 2.2.4. operations of the circled items are described below. figure 2.2.12 shows the operation timing, and figure 2.2.13 shows the set-up procedure. note: j = i C 1, but j = 4 when i = 0. (1) setting the count start flag to 1 causes the counter to count the falling edges of the count source. (2) if an underflow occurs, the content of the reload register is reloaded, and the count continues. at this time, the timer ai interrupt request bit goes to 1. (3) if switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) setting the count start flag to 0 causes the counter to hold its value and to stop. (5) if an overflow occurs, the content of the reload register is reloaded, and the count continues. at this time, the timer ai interrupt request bit goes to 1. operation table 2.2.4. choosed functions ffff 16 n 0000 16 time counter content (hex) n = reload register content (1) start count count start flag ? set to ?? by software ? timer ai interrupt request bit ? ? up/down flag ? ? set to ?? by software set to ?? by software (5) overflow cleared to ??when interrupt request is accepted, or cleared by software start count again aaaa (2) underflow aaaa aaaa (3) switch count cleared to 0 by software (4) stop count item item set-up set-up count source input signal to tai in (counting falling edges) input signal to tai in (counting rising edges) timer overflow (tb2/taj overflow) count operation type reload type free-run type factor for switching between up and down content of up/down flag input signal to tai out pulse output function no pulses output pulses output o o o o
193 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.13. set-up procedure of event counter mode, reload type selected selecting event counter mode and functions b7 b0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) up/down switching cause select bit 0 : up/down flag's content selection of event counter mode invalid in event counter mode (i = 0, 1) invalid when not using two-phase pulse signal processing(i = 2 to 4) count operation type select bit 0 : reload type 0 (must always be ??in event counter mode) count polarity select bit 0 : counts external signal's falling edge 01 00 00 0 b7 b0 0 00 up/down flag [address 0384 16 ] udf timer a0 up/down flag 0 : down count timer a1 up/down flag 0 : down count timer a2 up/down flag 0 : down count timer a3 up/down flag 0 : down count timer a4 up/down flag 0 : down count when not using the 2-phase pulse signal processing function, set the select bit to ?? setting one-shot start flag and trigger select register trigger select register [address 0383 16 ] trgsr one-shot start flag [address 0382 16 ] onsf timer a0 event/trigger select bit 0 0 : input on ta0 in is selected (note) b7 b6 b7 b0 b7 b0 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) b1 b0 timer a2 event/trigger select bit 0 0 : input on ta2 in is selected (note) b3 b2 timer a3 event/trigger select bit 0 0 : input on ta3 in is selected (note) b5 b4 timer a4 event/trigger select bit 0 0 : input on ta4 in is selected (note) b7 b6 note: set the corresponding port direction register to ?? setting divide ratio can be set to 0000 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 start count setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 setting up/down flag
194 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.14. operation timing of event counter mode, free run type selected 2.2.6 operation of timer a (event counter mode, free run type selected) in event counter mode, choose functions from those listed in table 2.2.5. operations of the circled items are described below. figure 2.2.14 shows the operation timing, and figure 2.2.15 shows the set-up procedure. note: j = i C 1, but j = 4 when i = 0 (1) setting the count start flag to 1 causes the counter to count the falling edges of the count source. (2) even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. at this time, the timer ai interrupt request bit goes to 1. (3) if switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. at this time, the timer ai interrupt request bit goes to 1. table 2.2.5. choosed functions operation ffff 16 n 0000 16 time counter content (hex) n = reload register content (1) start count count start flag ? ? timer ai interrupt request bit ? cleared to ??when interrupt request is accepted, or cleared by software ? up/down flag ? ? set to ?? by software (2) underflow (3) switch count (4) overflow set to ?? by software item item set-up set-up count source input signal to tai in (counting falling edges) input signal to tai in (counting rising edges) timer overflow (tb2/taj overflow) count operation type reload type free-run type factor for switching between up and down content of up/down flag input signal to tai out pulse output function no pulses output pulses output o o o o
195 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.15. set-up procedure of event counter mode, free run type selected setting divide ratio can be set to 0000 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 start count pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) selecting event counter mode and functions timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) up/down switching cause select bit 0 : up/down flag's content selection of event counter mode invalid in event counter mode (i = 0, 1) invalid when not using two-phase pulse signal processing(i = 2 to 4) count operation type select bit 1 : free-run type 0 (must always be ??in event counter mode) count polarity select bit 0 : counts external signal's falling edge b7 b0 01 00 00 1 b7 b0 0 00 setting up/down flag up/down flag [address 0384 16 ] udf timer a0 up/down flag 0 : down count timer a1 up/down flag 0 : down count timer a2 up/down flag 0 : down count timer a3 up/down flag 0 : down count timer a4 up/down flag 0 : down count when not using the 2-phase pulse signal processing function, be sure to set the select bit to ?? setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 setting one-shot start flag and trigger select register b7 b0 one-shot start flag [address 0382 16 ] onsf timer a0 event/trigger select bit 0 0 : input on ta0 in is selected (note) b7 b6 b7 b0 trigger select register [address 0383 16 ] trgsr timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) b1 b0 timer a2 event/trigger select bit 0 0 : input on ta2 in is selected (note) b3 b2 timer a3 event/trigger select bit 0 0 : input on ta3 in is selected (note) b5 b4 timer a4 event/trigger select bit 0 0 : input on ta4 in is selected (note) b7 b6 note: set the corresponding port direction register to ??
196 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.16. operation timing of 2-phase pulse signal process in event counter mode, normal mode selected 2.2.7 operation of timer a (2-phase pulse signal process in event counter mode, normal mode selected) in processing 2-phase pulse signals in event counter mode, choose functions from those listed in table 2.2.6. operations of the circled items are described below. figure 2.2.16 shows the operation timing, and figure 2.2.17 shows the set-up procedure. table 2.2.6. choosed functions note: timer a3 alone can be selected. timer a2 is solely used for normal processes, and timer a4 is solely used for 4 multiplication processes. (1) setting the count start flag to 1 causes the counter to count effective edges of the count source. (2) even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. at this time, the timer ai interrupt request bit goes to 1. (3) even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. at this time, the timer ai interrupt request bit goes to 1. ? the up count or down count conditions are as follows: if a rising edge is present at the tai in pin when the input signal level to the tai out pin is h, an up count is performed. if a falling edge is present at the tai in pin when the input signal level to the tai out pin is h, a down count is performed. operation note 0000 16 count start flag timer ai interrupt request bit ? ? ? ? ffff 16 counter content (hex) input pulse tai out ? ? ? ? tai in set to ?? by software cleared to ??when interrupt request is accepted, or cleared by software (1) start count (2) underflow (3) overflow time item count operation type 2-phase pulses process (note) set-up o o reload type free run type normal processing 4-multiplication processing
197 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.17. set-up procedure of 2-phase pulse signal process in event counter mode, normal mode selected setting divide ratio can be set to 0000 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 start count selecting event counter mode and functions 0 (must always be ??when using two-phase pulse signal processing) timer ai mode register (i= 2, 3) [address 0398 16 , 0399 16 ] taimr (i= 2, 3) 1 (must always be ??when using two-phase pulse signal processing) selection of event counter mode two-phase pulse signal processing operation select bit 0 : normal processing operation count operation type select bit 1 : free-run type 0 (must always be ??when using two-phase pulse signal processing) 0 (must always be ??when using two-phase pulse signal processing) b7 b0 01 00 10 01 two-phase pulse signal processing select bit b7 b0 up/down flag [address 0384 16 ] udf timer a2 two-phase pulse signal processing select bit 1 : two-phase pulse signal processing enabled timer a3 two-phase pulse signal processing select bit 1 : two-phase pulse signal processing enabled setting count start flag count start flag [address 0380 16 ] tabsr timer a2 count start flag timer a3 count start flag b7 b0
198 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.18. operation timing of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected 2.2.8 operation of timer a (2-phase pulse signal process in event counter mode, multiply-by-4 mode selected) in processing 2-phase pulse signals in event counter mode, choose functions from those listed in table 2.2.7. operations of the circled items are described below. figure 2.2.18 shows the operation timing, and figure 2.2.19 shows the set-up procedure. table 2.2.7. choosed functions note: timer a3 alone can be selected. timer a2 is solely used for normal processes, and timer a4 is solely used for 4- multiplication processes. (1) setting the count start flag to 1 causes the counter to count effective edges of the count source. (2) even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. at this time, the interrupt request bit goes to 1. (3) even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. at this time, the interrupt request bit goes to 1. ? the up count or down count conditions are as follows: operation note table 2.2.8. the up count or down count conditions time set to ?? by software 0000 16 count start flag timer ai interrupt request bit ? ? ? ? ffff 16 counter content (hex) input pulse tai out ? ? ? ? tai in (1) start count (2) underflow (3) overflow cleared to ??when interrupt request is accepted, or cleared by software item item set-up set-up count operation type reload type free run type o processing 2 phase pulses (note) o normal processing 4-multiplication processing up count input signal to the tai out pin input signal to the tai in pin down count input signal to the tai out pin input signal to the tai in pin ??level ??level rising falling rising falling ??level ??level ??level ??level rising falling falling rising ??level ??level
199 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.19. set-up procedure of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected setting divide ratio can be set to 0000 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 start count selecting event counter mode and functions 0 (must always be ??when using two-phase pulse signal processing) timer ai mode register (i= 3, 4) [address 0399 16 , 039a 16 ] taimr (i= 3, 4) 1 (must always be ??when using two-phase pulse signal processing) selection of event counter mode two-phase pulse signal processing operation select bit 1 : multiply-by-4 processing operation count operation type select bit 1 : free-run type 0 (must always be ??when using two-phase pulse signal processing) 0 (must always be ??when using two-phase pulse signal processing) b7 b0 01 00 10 11 two-phase pulse signal processing select bit b7 b0 up/down flag [address 0384 16 ] udf timer a3 two-phase pulse signal processing select bit 1 : two-phase pulse signal processing enabled timer a4 two-phase pulse signal processing select bit 1 : two-phase pulse signal processing enabled setting count start flag count start flag [address 0380 16 ] tabsr timer a3 count start flag timer a4 count start flag b7 b0
200 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.2.9 operation of timer a (one-shot timer mode) figure 2.2.20. operation timing of one-shot mode in one-shot timer mode, choose functions from those listed in table 2.2.9. operations of the circled items are described below. figure 2.2.20 shows the operation timing, and figure 2.2.21 shows the set-up procedure. operation note: j = i C 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. (1) setting the one-shot start flag to 1 with the count start flag set to 1 causes the counter to perform a down count on the count source. at this time, the tai out pin outputs an h level. (2) the instant the value of the counter becomes 0000 16 , the tai out pin outputs an l level, and the counter reloads the content of the reload register and stops counting. at this time, the timer ai interrupt request bit goes to 1. (3) if a trigger occurs while a count is in progress, the counter reloads the value in the reload register again and continues counting. the reload timing is in step with the next count source input after the trigger. (4) setting the count start flag to 0 causes the counter to stop and to reload the content of the reload register. also, the tai out pin outputs an l level. at this time, the timer ai interrupt request bit goes to 1. table 2.2.9. choosed functions item count source pulse output function count start condition set-up o o o internal count source (f 1 / f 8 / f 32 / fc 32 ) no pulses output pulses output external trigger input (falling edge of input signal to the tai in pin) external trigger input (rising edge of input signal to the tai in pin) timer overflow (tb2/taj/tak overflow) writing ??to the one-shot start flag ffff 16 n 0001 16 timer ai interrupt request bit counter content (hex) n = reload register content reload one-shot pulse output from tai out pin ? 1 / f i x (n) ? time reload 1 / f i x (n+1) write signal to one-shot start flag ? ? count start flag ? ? (1) start count cleared to ??when interrupt request is accepted, or cleared by software (2) stop count (3) start count (4) stop count start count reload set to ?? by software cleared to ?? by software
201 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.21. set-up procedure of one-shot mode pulse output function select bit 1 : pulse is output selecting one-shot timer mode and functions timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) external trigger select bit when internal is selected, this bit can be ??or ? selection of one-shot timer mode b7 b0 10 01 0 0 (must always be ??in one-shot timer mode) count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 trigger select bit 0 : when the one-shot start flag is set ? count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32 setting one-shot timer's time can be set to 0001 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 start count setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 setting one-shot start flag one-shot start flag [address 0382 16 ] onsf timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag b7 b0 setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0 clearing timer ai interrupt request bit timer ai interrupt control register [address 0055 16 to 0059 16 ] taiic (i=0 to 4) interrupt request bit b7 b0 0 refer to 'precaution for timer a (one-shot timer mode)'
202 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in one-shot timer mode, choose functions from those listed in table 2.2.10. operations of the circled items are described below. figure 2.2.22 shows the operation timing, and figure 2.2.23 shows the set-up procedure. 2.2.10 operation of timer a (one-shot timer mode, external trigger selected) figure 2.2.22. operation timing of one-shot mode, external trigger selected operation note: j = i C 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. (1) if the tai in pin input level changes from l to h with the count start flag set to 1, the counter performs a down count on the count source. at this time, the tai out pin output level goes to h level. (2) if the value of the counter becomes 0000 16 , the tai out pin outputs an l level, and the counter reloads the content of the reload register and stops counting. at this time, the timer ai interrupt request bit goes to 1. (3) if a trigger occurs while a count is in progress, the counter reloads the value of the reload register again and continues counting. the reload timing is in step with the next count source input after the trigger. (4) setting the count start flag to 0 causes the counter to stop and to reload the content of the reload register. also, the tai out pin outputs an l level. at this time, the timer ai interrupt request bit goes to 1. table 2.2.10. choosed functions item count source pulse output function count start condition set-up o o o internal count source (f 1 / f 8 / f 32 / fc 32 ) no pulses output pulses output external trigger input (falling edge of input signal to the tai in pin) external trigger input (rising edge of input signal to the tai in pin) timer overflow (tb2/taj/tak overflow) writing ??to the one-shot start flag ffff 16 n 0001 16 timer ai interrupt request bit counter content (hex) n = reload register content reload reload (4) stop count one-shot pulse output from tai out pin ? 1 / fi x (n) ? 1 / fi x (n+1) tai in pin input signal ? ? ? cleared to ??when interrupt request is accepted, or cleared by software ? count start flag ? ? (2) stop count (1) start count (3) start count time reload start count set to ?? by software trigger during count cleared to ?? by software
203 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.23. set-up procedure of one-shot mode, external trigger selected setting one-shot timer's time can be set to 0001 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 start count setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 pulse output function select bit 1 : pulse is output selecting one-shot timer mode and functions timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) external trigger select bit 1 : rising edge of tai in pin's input signal selection of one-shot timer mode b7 b0 10 11 1 0 (must always be ??in one-shot timer mode) count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 trigger select bit 1 : selected by event/trigger select bit 0 setting event/trigger select bit trigger select register [address 0383 16 ] trgsr one-shot start flag [address 0382 16 ] onsf timer a0 event/trigger select bit 0 0 : input on ta0 in is selected (note) b7 b6 b7 b0 b7 b0 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) b1 b0 timer a2 event/trigger select bit 0 0 : input on ta2 in is selected (note) b3 b2 timer a3 event/trigger select bit 0 0 : input on ta3 in is selected (note) b5 b4 timer a4 event/trigger select bit 0 0 : input on ta4 in is selected (note) b7 b6 note: set the corresponding port direction register to ?? count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32 setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0 clearing timer ai interrupt request bit timer ai interrupt control register [address 0055 16 to 0059 16 ] taiic (i=0 to 4) interrupt request bit b7 b0 0 refer to 'precaution for timer a (one-shot timer mode)'
204 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in pulse width modulation mode, choose functions from those listed in table 2.2.11. operations of the circled items are described below. figure 2.2.24 shows the operation timing, and figure 2.2.25 shows the set-up procedure. 2.2.11 operation of timer a (pulse width modulation mode, 16-bit pwm mode selected) figure 2.2.24. operation timing of pulse width modulation mode, 16-bit pwm mode selected note: j = i C 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. table 2.2.11. choosed functions (1) if the tai in pin input level changes from l to h with the count start flag set to 1, the counter performs a down count on the count source. also, the tai out pin outputs an h level. (2) the tai out pin output level changes from h to l when a set time period elapses. at this time, the timer ai interrupt request bit goes to 1. (3) the counter reloads the content of the reload register every time pwm pulses are output for one cycle, and continues counting. (4) setting the count start flag to 0 causes the counter to hold its value and to stop. also, the tai out outputs an l level. ? the period of pwm pulses becomes (2 16 C 1)/fi, and the h level pulse width becomes n/fi. if the timer ai register is set to 0000 16 , the pulse width modulator does not work, and the tai out pin output level remains at l. (fi : frequency of the count source f 1 , f 8 , f 32 , f c32 ; n : value of the timer) operation note item count source pwm mode count start condition set-up o o o internal count source (f 1 / f 8 / f 32 / fc 32 ) 16-bit pwm 8-bit pwm external trigger input (falling edge of input signal to the tai in pin) external trigger input (rising edge of input signal to the tai in pin) timer overflow (tb2/taj/tak overflow) count source ta iin pin input signal pwm pulse output from ta iout pin timer ai interrupt request bit count start flag 1 / f i x (2 ?) 16 conditions: reload register = 0003 16 , external trigger (rising edge of tai in pin input signal) is selected trigger is not generated by this signal ? ? ? ? ? ? cleared to ??when interrupt request is accepted, or cleared by software 1 / f i x n ? ? set to ?? by software (1) start count (2) output level ??to ? note: n = 0000 16 to fffe 16 (3) one period is complete (4) stop count cleared to ?? by software
205 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.25. set-up procedure of pulse width modulation mode, 16-bit pwm mode selected setting pwm pulse's ??level width can be set to 0000 16 to fffe 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 start count setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 setting event/trigger select bit one-shot start flag [address 0382 16 ] onsf timer a0 event/trigger select bit 0 0 : input on ta0 in is selected (note 2) b7 b6 b7 b0 b7 b0 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note 2) b1 b0 timer a2 event/trigger select bit 0 0 : input on ta2 in is selected (note 2) b3 b2 timer a3 event/trigger select bit 0 0 : input on ta3 in is selected (note 2) b5 b4 timer a4 event/trigger select bit 0 0 : input on ta4 in is selected (note 2) b7 b6 note 2: set the corresponding port direction register to ?? trigger select register [address 0383 16 ] trgsr 1 (must always be ??in pwm mode) selecting pwm mode and functions timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) external trigger select bit 1 : rising edge of tai in pin's input signal (note 1) selection of pwm mode b7 b0 11 11 1 16/8-bit pwm mode select bit 0 : functions as a 16-bit pulse width modulator b7 b6 count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 trigger select bit 1 : selected by event/trigger select register 0 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32 setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0 note 1: set the corresponding port direction register to ?? clearing timer ai interrupt request bit timer ai interrupt control register [address 0055 16 to 0059 16 ] taiic (i=0 to 4) interrupt request bit b7 b0 0 refer to 'precaution for timer a (pulse width modulation mode)'
206 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.2.12 operation of timer a (pulse width modulation mode, 8-bit pwm mode selected) figure 2.2.26. operation timing of pulse width modulation mode, with 8-bit pwm mode selected in pulse width modulation mode, choose functions from those listed in table 2.2.12. operations of the circled items are described below. figure 2.2.26 shows the operation timing, and figure 2.2.27 shows the set-up procedure. table 2.2.12. choosed functions note: j = i C 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. (1) if the tai in pin input level changes from h to l with the count start flag set to 1, the counter performs a down count on the count source. also, the tai out pin outputs an h level. (2) the tai out pin output level changes from h to l when a set time period elapses. at this time, the timer ai interrupt request bit goes to 1. (3) the counter reloads the content of the reload register every time pwm pulses are output for one cycle, and continues counting. (4) setting the count start flag to 0 causes the counter to hold its value and to stop. also, the tai out pin outputs an l level. ? the period of pwm pulses becomes (m + 1) x (2 8 C 1) / fi, and the h level pulse width becomes n x (m + 1) / fi. if 00 16 is set in the eight higher-order bits of the timer ai register, the pulse width modulator does not work, and the tai out pin output level remains at l. (fi : frequency of the count source f 1 , f 8 , f 32 , fc 32 ; n : value of the timer) ? when a trigger is generated, the tai out pin outputs l level of same amplitude as h level of the set pwm pulse, after which it starts pwm pulse output. operation note item count source pwm mode count start condition set-up o o o internal count source (f 1 / f 8 / f 32 / fc 32 ) 16-bit pwm 8-bit pwm external trigger input (falling edge of input signal to the tai in pin) external trigger input (rising edge of input signal to the tai in pin) timer overflow (tb2/taj/tak overflow) count source (note 1) reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of tai in pin input signal) is selected 1 / f i x (m + 1) x (2 ?1) 8 ta iin pin input underflow signal of 8-bit prescaler (note 2) pwm pulse output from ta iout pin ? ? ? ? timer ai interrupt request bit aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa h l 1 0 note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to fe 16 ; n = 00 16 to fe 16 . 1 / f i x (m + 1) x n count start flag 1 0 (1) start count (2) output level h to l cleared to 0 when interrupt request is accepted, or cleared by software (3) (4) stop count 1 / f i x (m+1) conditions: one period is complete
207 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.2.27. set-up procedure of pulse width modulation mode, 8-bit pwm mode selected start count setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag b7 b0 setting pwm pulse's period and ??level width can be set to 00 16 to fe 16 b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 timer a1 register [address 0389 16 , 0388 16 ] ta1 timer a2 register [address 038b 16 , 038a 16 ] ta2 timer a3 register [address 038d 16 , 038c 16 ] ta3 timer a4 register [address 038f 16 , 038e 16 ] ta4 can be set to 00 16 to fe 16 1 (must always be ??in pwm mode) selecting pwm mode and function timer ai mode register (i=0 to 4) [address 0396 16 to 039a 16 ] taimr (i=0 to 4) external trigger select bit 0 : falling edge of tai in pin's input signal (note1) selection of pwm mode b7 b0 11 01 1 16/8-bit pwm mode select bit 1: functions as an 8-bit pulse width modulator b7 b6 count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 trigger select bit 1 : selected by event/trigger select register 1 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2s 976.56s 00 01 10 11 f 1 f 8 f 32 f c32 setting event/trigger select bit one-shot start flag [address 0382 16 ] onsf timer a0 event/trigger select bit 0 0 : input on ta0 in is selected (note 2) b7 b6 b7 b0 trigger select register [address 0383 16 ] trgsr b7 b0 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note 2) b1 b0 timer a2 event/trigger select bit 0 0 : input on ta2 in is selected (note 2) b3 b2 timer a3 event/trigger select bit 0 0 : input on ta3 in is selected (note 2) b5 b4 timer a4 event/trigger select bit 0 0 : input on ta4 in is selected (note 2) b7 b6 note 2: set the corresponding port direction register to ?? setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0 note 1: set the corresponding port direction register to ?? clearing timer ai interrupt request bit timer ai interrupt control register [address 0055 16 to 0059 16 ] taiic (i=0 to 4) interrupt request bit b 7 b0 0 refer to 'precaution for timer a (pulse width modulation mode)'
208 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.2.13 precautions for timer a (timer mode) figure 2.2.28. reading timer ai register (1) to clear reset, the count start flag is set to 0. set a value in the timer ai register, then set the flag to 1. (2) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing shown in figure 2.2.28 gets ffff 16 . reading the timer ai register after setting a value in the timer ai regis- ter with a count halted but before the counter starts counting gets a proper value. 2 1 0 n n ?1 counter value (hex.) 2 1 0 ffff n ?1 read value (hex.) reload time n = reload register content
209 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) to clear reset, the count start flag is set to 0. set a value in the timer ai register, then set the flag to 1. (2) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing shown in figure 2.2.29 gets ffff 16 by underflow or 0000 16 by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts count- ing gets a proper value. (3) please note the standards for the differences between the 2 pulses used in the 2-phase pulse signals input signals to the tai in pin and tai out pin (i = 2, 3, 4), as shown in figure 2.2.30. (4) when free run type is selected, if count is stopped, set a value in the timer ai register again. 2.2.14 precautions for timer a (event counter mode) figure 2.2.30. standard of 2-phase pulses figure 2.2.29. reading timer ai register 210 n n ?1 counter value (hex.) 210 ffff read value (hex.) reload time n = reload register content (1) down count fffd fffe ffff n n + 1 counter value (hex.) fffd fffe ffff 0000 n + 1 read value (hex.) aa aa reload time n = reload register content (2) up count n e 1 t1 t2 t3 ta2 out ta3 out ta4 out ta2 in ta3 in ta4 in t1 (min.) t2, t3 (min.) vcc = 5v, f(x in ) = 10mhz 800ns 200ns t1 (min.) t2, t3 (min.) vcc = 3v, f(x in ) = 7mhz, one-wait 2s 500ns
210 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) to clear reset, the count start flag is set to 0. set a value in the timer ai register, then set the flag to 1. (2) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the tai out pin outputs l level. ? the interrupt request is generated and the timer ai interrupt request bit goes to 1. (3) the output from the one-shot timer synchronizes with the count source generated internally. therefore, when an external trigger has been selected, a delay of one cycle of the maximum count source occurs between the trigger input to the tai in pin and the one-shot timer output. (4) the timer ai interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (5) if a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. to generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred. 2.2.15 precautions for timer a (one-shot timer mode) figure 2.2.31. one-shot timer delay note: the above applies when an external trigger (falling edge of tai in pin input signal) is selected. tai in pin input signal ? ? count source trigger input start one-shot pulse output one-shot pulse output from tai out pin
211 timer a m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) to clear reset, the count start flag is set to 0. set a value in the timer ai register, then set the flag to 1. (2) the timer ai interrupt request bit becomes 1 if setting operation mode of the timer in compli- ance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (3) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the tai out pin is outputting an h level in this instance, the output level goes to l, and the timer ai interrupt request bit goes to 1. if the tai out pin is outputting an l level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes 1. 2.2.16 precautions for timer a (pulse width modulation mode)
212 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.3 timer b 2.3.1 overview the following is an overview for timer b, a 16-bit timer. (1) mode timer b operates in one of three modes: (a) timer mode the internal count source is counted. ? operation in timer mode ...................................................................................................... ..... p216 (b) event counter mode the number of pulses coming from outside and the number of the timer overflows are counted. ? operation in event counter mode ............................................................................................. p 218 (c) pulse period measurement/pulse width measurement mode external pulse period or external pulse widths are measured. if pulse period measurement mode is selected, the periods of input pulses are continuously measured. if pulse width measurement mode is selected, widths of h level pulses and those of l level pulses are continuously measured. ? operation in pulse period measurement mode ........................................................................ p220 ? operation in pulse width measurement mode .......................................................................... p222 (2) count source an internal count source can be selected from f 1 , f 8 , f 32 , and f c32 . f 1 , f 8 , and f 32 are clocks obtained by dividing the cpu main clock by 1, 8, and 32 respectively. f c32 is the clock obtained by dividing the cpu secondary clock by 32. (3) frequency division ratio the frequency division ratio equals [the value set in the timer register + 1]. the counter underflows when a count source equal to a frequency division ratio is input, and an interrupt request occurs. (4) reading the timer in timer mode or event counter mode, the count value at the time of reading the timer register will be read. read the register in 16-bit increments. in both the pulse period measurement mode and pulse width measurement mode, an indeterminate value is read until the second effective edge is input after a count is started, otherwise, the measurement results are read. (5) writing to the timer when writing to the timer register while a count is in progress, the value is written only to the reload register. when writing to the timer register while a count has stopped, the value is written both to the reload register and the count. write the value in 16-bit increments. the timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode.
213 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (6) input to the timer and the direction register to input an external signal to the timer, set the direction register of the relevant port to input. (7) pins related to timer b (a) tb0 in , tb1 in , tb2 in input pins to timer b. (8) registers related to timer b figure 2.3.1 shows the memory map of timer b-related registers. figures 2.3.2 and 2.3.3 show timer b-related registers. figure 2.3.1. memory map of timer b-related registers 005a 16 005b 16 005c 16 0380 16 0381 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 039b 16 039c 16 039d 16 timer b0 (tb0) timer b1 (tb1) timer b2 (tb2) count start flag (tabsr) clock prescaler reset flag (cpsrf) timer b1 interrupt control register (tb1ic) timer b0 interrupt control register (tb0ic) timer b2 interrupt control register (tb2ic) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr)
214 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.3.2. timer b-related registers (1) t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t s y m b o l b i t n a m e f u n c t i o n w r b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : t i m e r m o d e 0 1 : e v e n t c o u n t e r m o d e 1 0 : p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e 1 1 : i n h i b i t e d b 1 b 0 t c k 1 m r 3 m r 2 m r 1 t m o d 1 m r 0 t m o d 0 t c k 0 f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e c o u n t s o u r c e s e l e c t b i t ( f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e ) o p e r a t i o n m o d e s e l e c t b i t ( n o t e 1 ) ( n o t e 2 ) n o t e 1 : t i m e r b 0 . n o t e 2 : t i m e r b 1 , t i m e r b 2 .
215 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.3.3. timer b-related registers (2) symbol address when reset tabsr 0380 16 00 16 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? cpsr nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r ?pulse period / pulse width measurement mode measures a pulse period or width ?timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set ?event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note: read and write data in 16-bit units. function
216 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in timer mode, choose functions from those listed in table 2.3.1. operations of the circled items are described below. figure 2.3.4 shows the operation timing, and figure 2.3.5 shows the set-up procedure. 2.3.2 operation of timer b (timer mode) operation table 2.3.1. choosed functions (1) setting the count start flag to 1 causes the counter to perform a down count on the count source. (2) if an underflow occurs, the content of the reload register is reloaded, and the counter contin- ues counting. at this time, the timer bi interrupt request bit goes to 1. (3) setting the count start flag to 0 causes the counter to hold its value and to stop. figure 2.3.4. operation timing of timer mode item count source set-up o internal count source (f 1 / f 8 / f 32 / fc 32 ) ffff 16 n 0000 16 time count start flag timer bi interrupt request bit ? ? counter content (hex) n = reload register content set to ?? by software ? ? set to ?? by software cleared to ?? by software (2) underflow (3) stop count (1) start count cleared to ??when interrupt request is accepted, or cleared by software start count again
217 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.3.5. set-up procedure of timer mode setting divide ratio can be set to 0000 16 to ffff 16 b7 b0 (b15) (b8) b7 b0 timer b0 register [address 0391 16 , 0390 16 ] tb0 timer b1 register [address 0393 16 , 0392 16 ] tb1 timer b2 register [address 0395 16 , 0394 16 ] tb2 start count setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0 setting count start flag count start flag [address 0380 16 ] tabsr timer b0 count start flag timer b1 count start flag timer b2 count start flag b7 b0 selecting timer mode and functions invalid in timer mode can be ??or ? timer bi mode register (i=0 to 2) [address 039b 16 to 039d 16 ] tbimr (i=0 to 2) fixed to ??in timer mode ( i = 0) this bit can neither be set nor reset (i = 1, 2) selection of timer mode b7 b0 00 invalid in timer mode count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2s 976.56s 00 01 10 11 f 1 f 8 f 32 f c32
218 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in event counter mode, choose functions from those listed in table 2.3.2. operations of the circled items are described below. figure 2.3.6 shows the operation timing, and figure 2.3.7 shows the set-up procedure. 2.3.3 operation of timer b (event counter mode) operation table 2.3.2. choosed functions note: j = i C 1, but j = 2 when i = 0 figure 2.3.6. operation timing of event counter mode (1) setting the count start flag to 1 causes the counter to count the falling edges of the count source. (2) if an underflow occurs, the content of the reload register is reloaded, and the count continues. at this time, the timer bi interrupt request bit goes to 1. (3) setting the count start flag to 0 causes the counter to hold its value and to stop. item set-up count source input signal to the tbi in pin (counting falling edges) timer overflow(tbj overflow) o input signal to the tbi in pin (counting rising edges) input signal to the tbi in pin (counting rising edges and falling edges) ffff 16 n 0000 16 time count start flag timer bi interrupt request bit ? ? counter content (hex) n = reload register content set to ?? by software ? ? set to ?? by software cleared to ?? by software (1) start count (2) underflow (3) stop count cleared to ??when interrupt request is accepted, or cleared by software start count again
219 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.3.7. set-up procedure of event counter mode setting divide ratio can be set to 0000 16 to ffff 16 (n) b7 b0 (b15) (b8) b7 b0 timer b0 register [address 0391 16 , 0390 16 ] tb0 timer b1 register [address 0393 16 , 0392 16 ] tb1 timer b2 register [address 0395 16 , 0394 16 ] tb2 start count setting count start flag count start flag [address 0380 16 ] tabsr timer b0 count start flag timer b1 count start flag timer b2 count start flag b7 b0 selecting event counter mode and functions timer bi mode register (i=0 to 2) [address 039b 16 to 039d 16 ] tbimr (i=0 to 2) fixed to ??in event counter mode ( i = 0) this bit can neither be set nor reset (i = 1, 2) selection of event counter mode b7 b0 01 invalid in event counter mode event clock select 0 : input from tbi in pin (note) 0 0 0 count polarity select bit 0 0 : counts external signal falling edges b3 b2 note: set the corresponding port direction register to ??
220 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in pulse period/pulse width measurement mode, choose functions from those listed in table 2.3.3. op- erations of the circled items are described below. figure 2.3.8 shows the operation timing, and figure 2.3.9 shows the set-up procedure. 2.3.4 operation of timer b (pulse period measurement mode) figure 2.3.8. operation timing of pulse period measurement mode table 2.3.3. choosed functions operation note (1) setting the count start flag to 1 causes the counter to start counting the count source. (2) if a measurement pulse changes from h to l, the value of the counter goes to 0000 16 , and measurement is started. in this instance, an indeterminate value is transferred to the reload register. the timer bi interrupt request is not generated. (3) if a measurement pulse changes from h to l again, the value of the counter is transferred to the reload register, and the timer bi interrupt request bit goes to 1. then the value of the counter becomes 0000 16 , and the measurement is started again. ? the timer bi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer bi is overflowed. the factor of interrupt request can be determined by use of the timer bi overflow flag within the interrupt routine. ? the value of the counter at the beginning of a count is indeterminate. thus there can be in- stances in which the timer bi overflow flag goes to 1 immediately after a count is performed. ? the timer bi overflow flag goes to 0 if timer bi mode register is written to when the count start flag is 1. this flag cannot be set to 1 by software. item set-up count source internal count source (f 1 / f 8 / f 32 / fc 32 ) pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) o pulse period measurement (interval between measurement pulse falling edge to falling edge) pulse period measurement (interval between measurement pulse rising edge to rising edge) o measurement mode count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? ? transfer (indeterminate value) reload register ? counter transfer timing ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. measurement of pulse time interval from falling edge to falling edge transfer (measured value) cleared to ??when interrupt request is accepted, or cleared by software (1) start count (2) start measurement (3) start measurement again (note 1) (note 1) (note 2)
221 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.3.9. set-up procedure of pulse period measurement mode setting count start flag count start flag [address 0380 16 ] tabsr timer b0 count start flag timer b1 count start flag timer b2 count start flag b7 b0 selecting pulse period / pulse width measurement mode and functions timer bi mode register (i=0 to 2) [address 039b 16 to 039d 16 ] tbimr (i=0 to 2) fixed to ??in pulse period/pulse width measurement mode (i = 0) this bit can neither be set nor reset (i = 1,2) selection of pulse period / pulse width measurement mode b7 b0 10 timer bi overflow flag 0 : timer did not overflow 1 : timer has overflowed count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 measurement mode select bit 0 0 : pulse period measurement (interval between measurement pulse falling edge to falling edge) b3 b2 0 0 clearing overflow flag timer bi mode register (i=0 to 2) [address 039b 16 to 039d 16 ] tbimr (i=0 to 2) b7 b0 timer bi overflow flag 0 : timer did not overflow 0 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2s 976.56s 00 01 10 11 f 1 f 8 f 32 f c32 start count setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0
222 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in pulse period/pulse width measurement mode, choose functions from those listed in table 2.3.4. op- erations of the circled items are described below. figure 2.3.10 shows the operation timing, and figure 2.3.11 shows the set-up procedure. 2.3.5 operation of timer b (pulse width measurement mode) figure 2.3.10. operation timing of pulse width measurement mode operation note table 2.3.4. choosed functions (1) setting the count start flag to 1 causes the counter to start counting the count source. (2) if an effective edge of a pulse to be measured is input, the value of the counter goes to 0000 16 , and measurement is started. in this instance, an indeterminate value is transferred to the reload register. the timer bi interrupt request is not generated. (3) if an effective edge of a pulse to be measured is input again, the value of the counter is transferred to the reload register, and the timer bi interrupt request bit goes to 1. then the value of the counter becomes 0000 16 , and measurement is started again. ? the timer bi interrupt request bit goes to 1 when an effective edge of a pulse to be measured is input or timer bi overflows. the factor of interrupt request can be determined by use of the timer bi overflow flag within the interrupt routine. ? the value of the counter at the beginning of a count is indeterminate. thus there can be in- stances in which the timer bi overflow flag goes to 1 immediately after a count is performed. ? the timer bi overflow flag goes to 0 if timer bi mode register is written to when the count start flag is 1. this flag cannot be set to 1 by software. item set-up count source internal count source (f 1 / f 8 / f 32 / fc 32 ) pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) o pulse period measurement (interval between measurement pulse falling edge to falling edge) pulse period measurement (interval between measurement pulse rising edge to rising edge) o measurement mode measurement pulse ? count source reload register ? counter transfer timing count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) (note 2) (1) start count (2) start measurement (3) start measurement again cleared to ??when interrupt request is accepted, or cleared by software transfer (indeterminate value) transfer(measured value) (note 1)
223 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.3.11. set-up procedure of pulse width measurement mode start count setting count start flag count start flag [address 0380 16 ] tabsr timer b0 count start flag timer b1 count start flag timer b2 count start flag b7 b0 selecting pulse period / pulse width measurement mode and functions timer bi mode register (i=0 to 2) [address 039b 16 to 039d 16 ] tbimr (i=0 to 2) fixed to ??in pulse period/pulse width measurement mode (i = 0) this bit can neither be set nor reset (i = 1, 2) selection of pulse period / pulse width measurement mode b7 b0 10 timer bi overflow flag 0 : timer did not overflow 1 : timer has overflowed count source select bit 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 measurement mode select bit 1 0 : pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) b3 b2 0 1 clearing overflow flag timer bi mode register (i=0 to 2) [address 039b 16 to 039d 16 ] tbimr (i=0 to 2) b7 b0 timer bi overflow flag 0 : timer did not overflow 0 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2s 976.56s 00 01 10 11 f 1 f 8 f 32 f c32 setting clock prescaler reset flag (this function is effective when f c32 is selected as the count source. reset the prescaler for generating f c32 by dividing the x cin by 32.) clock prescaler reset flag [address 0381 16 ] cpsrf clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? b7 b0
224 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) to clear reset, the count start flag is set to 0. set a value in the timer bi register, then set the flag to 1. (2) reading the timer bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing shown in figure 2.3.12 gets ffff 16 . reading the timer bi register after setting a value in the timer bi regis- ter with a count halted but before the counter starts counting gets a proper value. 2.3.6 precautions for timer b (timer mode, event counter mode) figure 2.3.12. reading timer bi register 21 0 n n ?1 counter value (hex.) 21 0 ffff n ?1 read value (hex.) reload time n = reload register content
225 timer b m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) the timer bi interrupt request bit goes to ??when an effective edge of a measurement pulse is input or timer bi is overflowed. the factor of interrupt request can be determined by use of the timer bi overflow flag within the interrupt routine. (2) if the timer overflow occurs simultaneously with the input of a measurement pulse, and if the interrupt factor cannot be determined from the timer bi overflow flag, connect the timers and count the number of overflows. (3) when reset, the timer bi overflow flag goes to ?? this flag can be set to ??by writing to the timer bi mode register when the count start flag is ?? (4) use the timer bi interrupt request bit to detect only overflows. use the timer bi overflow flag only to determine the interrupt factor within the interrupt routine. (5) when the first effective edge is input after a count is started, an indeterminate value is trans- ferred to the reload register. at this time, timer bi interrupt request is not generated. (6) the value of the counter is indeterminate at the beginning of a count. therefore the timer bi overflow flag may go to ??immediately after a count is started. (7) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to ?? (8) if the input signal to the tbi in pin is affected by noise, precise measurement may not be performed in some cases. it is recommended to see that measurements fall within a specific range by use of software. (9) for pulse width measurement, pulse widths are successively measured. use software to check whether the measurement result is an ??level width or an ??level width. 2.3.7 precautions for timer b (pulse period/pulse width measurement mode)
226 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.4.1 overview clock-synchronous serial i/o carries out 8-bit data communications in synchronization with the clock. the following is an overview of the clock-synchronous serial i/o. (1) transmission/reception format 8-bit data (2) transfer rate if the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit rate generator division, becomes the transfer rate. the bit rate generator count source can be se- lected from the following: f 1 , f 8 , and f 32 . clocks f 1 , f 8 , and f 32 are derived by dividing the cpus main clock by 1, 8, and 32 respectively. furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the clk pin becomes the transfer rate. (3) error detection only overrun error can be detected. overrun error is an error that occurs when the next data is made ready before the reception buffer register is read. (4) how to deal with an error when receiving data, read an error flag and reception data simultaneously to determine which error has occurred. if the data read is erroneous, initialize the error flag and the uarti receive buffer register, then receive the data again. to initialize the uarti receive buffer register 1. set the receive enable bit to 0 (disable reception). 2. set the serial i/o mode select bit to 000 2 (invalid serial i/o). 3. set the serial i/o mode select bit. 4. set the receive enable bit to 1 again (enable reception). to transmit data again due to an error on the reception side, set the uarti transmit buffer register again, then transmit the data again. to set the uarti transmit buffer register again 1. set the serial i/o mode select bits to 000 2 (invalidate serial i/o). 2. set the serial i/o mode select bits again. 3. set the transmit enable bit to 1 (enable transmission), then set transmission data in the uarti transmit buffer register. (5) function selection for clock-synchronous serial i/o, the following functions can be selected: _______ _______ (a) cts/rts function _______ in the cts function, an external ic can start transmission/reception by inputting an l level to the _______ _______ cts pin. the cts pin input level is detected when transmission/reception starts. therefore, if the level is set to h during transmission/reception, it will stop from the next data. _______ _______ _______ the rts function informs an external ic that rts is reception-ready and has changed to l. rts goes to h at the falling edge of the transfer clock. _______ _______ the clock-synchronous serial i/o has three types of cts/rts functions to choose from: _______ _______ ? cts/rts functions disabled _______ _______ cts/rts pin is a programmable i/o port. _______ ? cts function only enabled _______ _______ _______ cts/rts pin performs the cts function. _______ ? rts function only enabled _______ _______ _______ cts/rts pin performs the rts function. 2.4 clock-synchronous serial i/o
227 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (b) function for choosing polarity this function switches the polarity of the transfer clock. the following operations are available: ? data is input at the falling edge of the transfer clock, and is output at the rising edge. ? data is input at the rising edge of the transfer clock, and is output at the falling edge. (c) function for choosing which bit to transmit first this function is to choose whether to transmit data from bit 0 or from bit 7. choose either of the following: ? lsb first data is transmitted from bit 0. ? msb first data is transmitted from bit 7. (d) function for choosing successive reception mode successive reception mode is a mode in which reading the receive buffer register makes the recep- tion-enabled status ready. in this mode, there is no need to write dummy data to the transmit buffer register so as to make the reception-enabled status ready. but at the time of starting reception, read the receive buffer register into a dummy manner. ? normal mode writing dummy data to the transmit buffer register makes the reception enabled status ready. ? successive reception mode reading the reception buffer register makes the reception-enabled status ready. (e) function for outputting transfer clock to multiple pins this function is to switch among pins to output the transfer clock. this function is effective only when selecting the internal clock. switching among pins for outputting the transfer clock allows data trans- mission to two external ics in a time-sharing manner. (f) function for choosing a transmission interrupt factor the timing to generate a transmission interrupt can be selected from the following: the instant the transmission buffer is emptied or the instant the transmission register is emptied. when transmis- sion buffer empty timing is selected, an interrupt occurs when transmitted data is moved from the transmission buffer to the transmission register. therefore, data can be transmitted in succession. when transmission register empty timing is selected, an interrupt occurs when data transmission is complete. following are some examples in which various functions (a) through (f) are selected: _______ ? transmission operation with: cts function, transmission at falling edge of transfer clock, lsb first, interrupt at instant transmission buffer is emptied; without transfer clock output to multiple pins function .................................................................................................................. .......... p232 _______ _______ ? transmission operation with: cts/rts function disabled, transmission at falling edge of transfer clock, lsb first, interrupt at instant transmission is completed; with transfer clock output to mul- tiple pins function (uart0 selection available) ....................................................................... p236 _______ ? reception with: rts function, reception at falling edge of transfer clock, lsb first, successive reception mode disabled; without transfer clock output to multiple pins function .............. p240
228 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (6) input to the serial i/o and the direction register to input an external signal to the serial i/o, set the direction register of the relevant port to input. (7) pins related to the serial i/o _______ ? cts 0 , cts 1 pins _______ input pins for the cts function ________ ? rts 0 , rts 1 pins _______ output pins for the rts function ? clk0, clk1 pins input/output pins for the transfer clock ? rxd0, rxd1 pins input pins for data ? txd0, txd1 pins output pins for data. ? clks1 pin output pin for transfer clock. can be used as transfer clock output pin in the transfer clock output to multiple pins function. (8) registers related to the serial i/o figure 2.4.1 shows the memory map of serial i/o-related registers, and figures 2.4.2 to 2.4.4 show serial i/o-related registers. figure 2.4.1. memory map of serial i/o-related registers uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) uart transmit/receive control register 2 (ucon) 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 0051 16 0052 16 0053 16 0054 16 uart0 transmit interrupt control register (s0tic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control regster(s1tic) uart1 receive interrupt control register(s1ric)
229 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.2. serial i/o-related registers (1) b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmission data symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate uarti bit rate generator b7 b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate function assuming that set value = n, brgi divides the count source by (n + 1) 00 16 to ff 16 values that can be set symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate b7 b0 (b15) (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note: bits 15 through 12 are set to ??when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 and 03a8 16 ) are set to ?00 2 ?or the receive enable bit is set to ?? (bit 15 is set to ??when bits 14 to 12 all are set to ??) bits 14 and 13 are also set to ??when the lower byte of the uarti receive buffer register (addresses 03a6 16 and 03ae 16 ) is read out. invalid invalid invalid oer fer per sum overrun error flag (note) framing error flag (note) parity error flag (note) error sum flag (note) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found reception data w r w r w r reception data nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ??
230 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.3. serial i/o-related registers (2) w r u a r t i t r a n s m i t / r e c e i v e m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t u i m r ( i = 0 , 1 )0 3 a 0 1 6 , 0 3 a 8 1 6 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e b i t s y m b o l m u s t b e f i x e d t o 0 0 1 0 0 0 : s e r i a l i / o i n v a l i d 0 1 0 : i n h i b i t e d 0 1 1 : i n h i b i t e d 1 1 1 : i n h i b i t e d b 2 b 1 b 0 c k d i r s m d 1 s m d 0 s e r i a l i / o m o d e s e l e c t b i t s m d 2 i n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t s t p s p r y p r y e s l e p p a r i t y e n a b l e b i t 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k s t o p b i t l e n g t h s e l e c t b i t o d d / e v e n p a r i t y s e l e c t b i t s l e e p s e l e c t b i t 0 : o n e s t o p b i t 1 : t w o s t o p b i t s 0 : p a r i t y d i s a b l e d 1 : p a r i t y e n a b l e d 0 : s l e e p m o d e d e s e l e c t e d 1 : s l e e p m o d e s e l e c t e d 1 0 0 : t r a n s f e r d a t a 7 b i t s l o n g 1 0 1 : t r a n s f e r d a t a 8 b i t s l o n g 1 1 0 : t r a n s f e r d a t a 9 b i t s l o n g 0 0 0 : s e r i a l i / o i n v a l i d 0 1 0 : i n h i b i t e d 0 1 1 : i n h i b i t e d 1 1 1 : i n h i b i t e d b 2 b 1 b 0 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k i n v a l i d v a l i d w h e n b i t 6 = 1 0 : o d d p a r i t y 1 : e v e n p a r i t y i n v a l i d i n v a l i d m u s t a l w a y s b e 0 f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) u a r t i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 s y m b o la d d r e s sw h e n r e s e t u i c 0 ( i = 0 , 1 )0 3 a 4 1 6 , 0 3 a c 1 6 0 8 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) t x e p t c l k 1 c l k 0 c r s c r d n c h c k p o l b r g c o u n t s o u r c e s e l e c t b i t t r a n s m i t r e g i s t e r e m p t y f l a g 0 : t r a n s m i t d a t a i s o u t p u t a t f a l l i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t r i s i n g e d g e 1 : t r a n s m i t d a t a i s o u t p u t a t r i s i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t f a l l i n g e d g e c l k p o l a r i t y s e l e c t b i t c t s / r t s f u n c t i o n s e l e c t b i t c t s / r t s d i s a b l e b i t d a t a o u t p u t s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 0 : l s b f i r s t 1 : m s b f i r s t 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) 0 : c t s / r t s f u n c t i o n e n a b l e d 1 : c t s / r t s f u n c t i o n d i s a b l e d ( p 4 7 a n d p 7 7 f u n c t i o n a s p r o g r a m m a b l e i / o p o r t ) 0 : t x d i p i n i s c m o s o u t p u t 1 : t x d i p i n i s n - c h a n n e l o p e n - d r a i n o u t p u t u f o r mt r a n s f e r f o r m a t s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 v a l i d w h e n b i t 4 = 0 0 : c t s f u n c t i o n i s s e l e c t e d ( n o t e 1 ) 1 : r t s f u n c t i o n i s s e l e c t e d ( n o t e 2 ) v a l i d w h e n b i t 4 = 0 0 : c t s f u n c t i o n i s s e l e c t e d ( n o t e 1 ) 1 : r t s f u n c t i o n i s s e l e c t e d ( n o t e 2 ) 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) 0 : t x d i p i n i s c m o s o u t p u t 1 : t x d i p i n i s n - c h a n n e l o p e n - d r a i n o u t p u t m u s t a l w a y s b e 0 b i t n a m e b i t s y m b o l m u s t a l w a y s b e 0 n o t e 1 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . n o t e 2 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . 0 : c t s / r t s f u n c t i o n e n a b l e d 1 : c t s / r t s f u n c t i o n d i s a b l e d ( p 4 7 a n d p 7 7 f u n c t i o n a s p r o g r a m m a b l e i / o p o r t ) w r
231 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.4. serial i/o-related registers (3) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register note: when using multiple pins to output the transfer clock, the following requirement must be met: ?uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? u0irs u1irs u0rrm u1rrm invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = ?? 0 : clock output to clk1 1 : clock output to clks1 reserved bit must always be ? must always be ? nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be ?? 0
232 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in transmitting data in clock-synchronous serial i/o mode, choose functions from those listed in table 2.4.1. operations of the circled items are described below. figure 2.4.5 shows the operation timing, and figures 2.4.6 and 2.4.7 show the set-up procedures. 2.4.2 operation of serial i/o (transmission in clock-synchronous serial i/o mode) note: this can be selected only when uart1 is used in combination with the internal clock. when this function is _______ _______ _______ _______ selected, uart1 cts/rts function cannot be utilized. set the uart1 cts/rts disable bit to 1. (1) setting the transmit enable bit to 1 and writing transmission data to the uarti transmit buffer register makes data transmissible status ready. ________ _______ (2) when input to the ctsi pin goes to l level, transmission starts (the ctsi pin must be controlled on the reception side). (3) in synchronization with the first falling edge of the transfer clock, transmission data held in the uarti transmit buffer register is transmitted to the uarti transmit register. at this time, the uarti transmit interrupt request bit goes to 1. also, the first bit of the transmission data is transmitted from the txdi pin. then the data is transmitted bit by bit from the lower order in synchronization with the falling edges. (4) when transmission of 1-byte data is completed, the transmit register empty flag goes to 1, which indicates that transmission is completed. the transfer clock stops at h level. (5) if the next transmission data is set in the uarti transmit buffer register while transmission is in progress (before the eighth bit has been transmitted), the data is transmitted in succession. operation table 2.4.1. choosed functions item item set-up set-up transfer clock source clk polarity internal clock (f 1 / f 8 / f 32 ) external clock (clki pin) cts function cts function enabled cts function disabled output transmission data at the falling edge of the transfer clock output transmission data at the rising edge of the transfer clock o o o transmission interrupt factor transmission buffer empty transmission complete output transfer clock to multiple pins (note) not selected selected o o transfer clock lsb first msb first o
233 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r example of wiring figure 2.4.5. operation timing of transmission in clock-synchronous serial i/o mode example of operation clki t x di ctsi clk r x d port microcomputer receiver side ic d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t clk stopped pulsing because transfer enable bit = ? tc = t clk = 2(n + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 32 ) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) ? ? ? ? ? ? ? ? ctsi transmit interrupt request bit (ir) ? ? cleared to ??when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 aaaaaaaaa (1) transmission enabled aaaaaaa (2) confirming cts aaaaaaa aaaaaaa (3) start transmission tc aaaaaaaaaa (4) transmission is complete aaaaaaaaa (5) transmit next data data is set to uarti transmit buffer register stopped pulsing because ctsi = h shown in ( ) are bit symbols. the above timing applies to the following settings: internal clock is selected. cts function is selected. clk polarity select bit = 0. transmit interrupt cause select bit = 0. transferred from uarti transmit buffer register to uarti transmit register
234 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.6. set-up procedure of transmission in clock-synchronous serial i/o mode (1) continued to the next page internal/external clock select bit 0 : internal clock setting uarti transmit/receive mode register (i=0, 1) uart0 transmit/receive mode register u0mr [address 03a0 16 ] uart1 transmit/receive mode register u1mr [address 03a8 16 ] invalid in clock synchronous i/o mode must be fixed to ?01? b7 b0 01 00 0 invalid in clock synchronous i/o mode invalid in clock synchronous i/o mode sleep select bit must be ??in clock synchronous i/o mode setting uarti transmit/receive control register 0 (i=0, 1) uart0 transmit/receive control register 0 u0c0 [address 03a4 16 ] uart1 transmit/receive control register 0 u1c0 [address 03ac 16 ] clk polarity select bit 0 : transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 00 00 brg count source select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 cts/rts function select bit (valid when bit 4 = ?? 0 : cts function is selected (note) cts/rts disable bit 0 : cts/rts function enabled transmit register empty flag 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) transfer format select bit 0 : lsb first note: set the corresponding port direction register to ??. data output select bit 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uart transmit/receive control register 2 ucon [address 03b0 16 ] uart0 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) clk/clks select bit 1 0 : normal mode (clk output is clk1 only) uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) valid when bit 5 = ?? fix ??to this bit. b7 b0 00 setting uart transmit/receive control register 2 00
235 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.7. set-up procedure of transmission in clock-synchronous serial i/o mode (2) start transmission when ctsi input level = ? setting uarti bit rate generator (i = 0, 1) uarti bit rate generator (i = 0, 1) [address 03a1 16 , 03a9 16 ] uibrg (i = 0, 1) can be set to 00 16 to ff 16 (note) b7 b0 note: write to uarti bit rate generator when transmission/reception is halted. transmission is complete continued from the previous page uart0 transmit/receive control register 1 u0c1 [address 03a5 16 ] uart1 transmit/receive control register 1 u1c1 [address 03ad 16 ] transmit enable bit 1 : transmission enabled b7 b0 1 transmission enabled writing transmit data uart0 receive buffer register [address 03a3 16 , 03a2 16 ] u0tb uart1 receive buffer register [address 03ab 16 , 03aa 16 ] u1tb setting transmission data b7 b0 b7 b0 (b15) (b8) uart0 transmit/receive control register 1 u0c1 [address 03a5 16 ] uart1 transmit/receive control register 1 u1c1 [address 03ad 16 ] b7 b0 transmit buffer empty flag 0 : data present in transmit buffer register 1 : no data present in transmit buffer register (writing next transmit data enabled) checking the status of uarti transmit /receive control register (i = 0, 1) writing next transmit data uart0 transmit buffer register [address 03a3 16 , 03a2 16 ] u0tb uart1 transmit buffer register [address 03ab 16 , 03aa 16 ] u1tb setting transmission data b7 b0 b7 b0 (b15) (b8)
236 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.4.3 operation of the serial i/o (transmission in clock-synchronous serial i/o mode, transfer clock output from multiple pins function selected) note 1: this can be selected only when uart1 is used in combination with the internal clock. when this function is _______ _______ _______ _______ selected, uart1 cts/rts function cannot be utilized. set the uart1 cts/rts disable bit to 1. (1) setting the transmit enable bit to 1 makes data transmissible status ready. (2) when transmission data is written to the uart1 transmit buffer register, transmission data held in the uart1 transmit buffer register is transmitted to the uart1 transmit register in synchronization with the first falling edge of the transfer clock. at this time, the first bit of the transmission data is transmitted from the txd1 pin. then the data is transmitted bit by bit from the lower order in synchronization with the falling edges of the transfer clock. (3) when transmission of 1-byte data is completed, the transmit register empty flag goes to 1, which indicates that the transmission is completed. the transfer clock stops at h level. at this time, the uart1 transmit interrupt request bit goes to 1. (4) setting clk/clks select bit 1 to 1 and setting clk/clks select bit 0 to 1 causes the clks1 pin to go to the transfer clock output pin. change the transfer clock output pin when transmission is halted. operation in transmitting data in clock-synchronous serial i/o mode, choose functions from those listed in table 2.4.2. operations of the circled items are described below. figure 2.4.8 shows the operation timing, and figures 2.4.9 and 2.4.10 show the set-up procedures. table 2.4.2. choosed functions item item set-up set-up transfer clock source clk polarity internal clock (f 1 / f 8 / f 32 ) external clock (clki pin) cts function cts function enabled cts function disabled output transmission data at the falling edge of the transfer clock output transmission data at the rising edge of the transfer clock o o o transmission interrupt factor transmission buffer empty transmission complete output transfer clock to multiple pins (note 1) not selected selected o o transfer clock lsb first msb first o
237 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r example of wiring example of operation figure 2.4.8. operation timing of transmission in clock-synchronous serial i/o mode, transfer clock output from multiple pins function selected microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 )in clk in clk note: this applies when performing only transmission with an internal clock selected in the clock synchronous serial i/o mode. transmit interrupt request bit ? ? cleared to ??when interrupt request is accepted, or cleared by software transmit buffer empty flag clk 1 txd 1 ? ? transmit enable bit ? ? transfer clock clks 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clk, clks select bit 1 ? ? ? ? clk, clks select bit 0 (1) transmission enabled (2) start transmission (3) transmission is complete (4) clock switched
238 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.9. set-up procedure of transmission in clock-synchronous serial i/o mode, transfer clock output from multiple pins function selected (1) internal/external clock select bit 0 : internal clock setting uart1 transmit/receive mode register uart1 transmit/receive mode register [address 03a8 16 ] u1mr invalid in clock synchronous i/o mode must be fixed to ?01 b7 b0 01 00 0 invalid in clock synchronous i/o mode invalid in clock synchronous i/o mode sleep select bit must be ??in clock synchronous i/o mode setting uart1 transmit/receive control register 0 uart1 transmit/receive control register 0 [address 03ac 16 ] u1c0 clk polarity select bit 0 : transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 1 00 brg count source select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = ? data output select bit 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output cts/rts disable bit 1 : cts/rts function disabled transmit register empty flag 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) transfer format select bit 0 : lsb first continued to the next page setting uart transmit/receive control register 2 uart transmit/receive control register 2 [address 03b0 16 ] ucon clk/clks select bit 1 1 : transfer clock output from multiple pins function selected uart0 transmit interrupt cause select bit 1 : transmission completed (txept = 1) clk/clks select bit 0 0 : clock output to clk1 1 : clock output to clks1 fix ??to this bit. b7 b0 1 1 0
239 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.10. set-up procedure of transmission in clock-synchronous serial i/o mode, transfer clock output from multiple pins function selected (2) setting uart1 bit rate generator uart1 bit rate generator [address 03a9 16 ] u1brg can be set to 00 16 to ff 16 (note) b7 b0 writing transmit data uart1 transmit buffer register [address 03ab 16 , 03aa 16 ] u1tb setting transmission data b7 b0 b7 b0 (b15) (b8) transmission enabled uart1 transmit/receive control register 1 [address 03ad 16 ] u1c1 transmit enable bit 1 : transmission enabled b7 b0 1 checking the status of uart1 transmit buffer register uart1 transmit/receive control register 1 [address 03ad 16 ] u1c1 b7 b0 transmit buffer empty flag 0 : data present in transmit buffer register 1 : no data present in transmit buffer register (writing next transmit data enabled) start transmission writing next transmit data uart1 transmit buffer register [address 03ab 16 , 03aa 16 ] u1tb setting transmission data b7 b0 b7 b0 (b15) (b8) transmission is complete continued from the previous page note: write to uarti bit rate generator when transmission/reception is halted.
240 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in receiving data in clock-synchronous serial i/o mode, choose functions from those listed in table 2.4.3. operations of the circled items are described below. figure 2.4.11 shows the operation timing, and fig- ures 2.4.12 and 2.4.13 show the set-up procedures. 2.4.4 operation of serial i/o (reception in clock-synchronous serial i/o mode) table 2.4.3. choosed functions note 1: this can be selected only when uart1 is used in combination with the internal clock. when this function is _______ _______ _______ _______ selected, uart1 cts/rts function cannot be utilized. set the uart1 cts/rts disable bit to 1. (1) writing dummy data to the uarti transmit buffer register, setting the receive enable bit to 1, and the transmit enable bit to 1, makes the data receivable status ready. at this time, the ________ output from the rtsi pin goes to l level, which informs the transmission side that the data receivable status is ready (output the transfer clock from the ic on the transmission side after _______ checking that the rts output has gone to l level). (2) in synchronization with the first rising edge of the transfer clock, the input signal to the rxdi pin is stored in the highest bit of the uarti receive register. then, data is taken in by shifting right the content of the uarti reception data in synchronization with the rising edges of the transfer clock. (3) when 1-byte data lines up in the uarti receive register, the content of the uarti receive register is transmitted to the uarti receive buffer register. the transfer clock stops at h level. at this time, the receive complete flag and the uarti receive interrupt request bit goes to 1. (4) the receive complete flag goes to 0 when the lower-order byte of the uarti receive buffer register is read. operation item item set-up set-up transfer clock source clk polarity internal clock (f 1 / f 8 / f 32 ) external clock (clki pin) rts function rts function enabled rts function disabled input reception data at the rising edge of the transfer clock input reception data at the falling edge of the transfer clock o o o continuous receive mode disabled enabled o output transfer clock to multiple pins (note 1) not selected selected o transfer clock lsb first msb first o
241 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r example of wiring figure 2.4.11. operation timing of reception in clock-synchronous serial i/o mode example of operation clki r x di rtsi clk t x d port microcomputer transmitter side ic 1 / f ext transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) rtsi ? ? ? ? ? ? ? ? receive enable bit (re) ? ? the above timing applies to the following settings: ?external clock is selected. ?rts function is selected. ?clk polarity select bit = ?? f ext : frequency of external clock make sure that the following conditions are met when the clki pin input =??before data reception ?transmit enable bit ? ? ?receive enable bit ? ? ?dummy data write to uarti transmit buffer register receive interrupt request bit (ir) ? ? cleared to ??when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. reception data is taken in transferred from uarti receive register to uarti receive buffer register (1) reception enabled (2) start reception (3) reception is complete read out from uarti receive buffer register transferred from uarti transmit buffer register to uarti transmit register (4) read of reception data dummy data is set in uarti transmit buffer register
242 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.12. set-up procedure of reception in clock-synchronous serial i/o mode (1) continued to the next page internal/external clock select bit 1 : external clock setting uarti transmit/receive mode register (i=0, 1) uart0 transmit/receive mode register u0mr [address 03a0 16 ] uart1 transmit/receive mode register u1mr [address 03a8 16 ] invalid in clock synchronous i/o mode must be fixed to ?01? b7 b0 01 00 1 invalid in clock synchronous i/o mode invalid in clock synchronous i/o mode sleep select bit must be ??in clock synchronous i/o mode setting uarti transmit/receive control register 0 (i=0, 1) uart0 transmit/receive control register 0 u0c0 [address 03a4 16 ] uart1 transmit/receive control register 0 u1c0 [address 03ac 16 ] clk polarity select bit 0 : transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 01 00 brg count source select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 cts/rts function select bit (valid when bit 4 = ?? 1 : rts function is selected cts/rts disable bit 0 : cts/rts function enabled transmit register empty flag 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) transfer format select bit 0 : lsb first data output select bit 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uart transmit/receive control register 2 ucon [address 03b0 16 ] uart0 continuous receive mode enable bit 0 : continuous receive mode disabled clk/clks select bit 1 0 : normal mode (clk output is clk1 only) uart1 continuous receive mode enable bit 0 : continuous receive mode disabled valid when bit 5 = ?? fix ??to this bit. b7 b0 00 setting uart transmit/receive control register 2 00
243 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.4.13. set-up procedure of reception in clock-synchronous serial i/o mode (2) writing dummy data uart0 transmit buffer register [address 03a3 16 , 03a2 16 ] u0tb uart1 transmit buffer register [address 03ab 16 , 03aa 16 ] u1tb setting dummy data b7 b0 b7 b0 (b15) (b8) checking completion of reception b7 b0 receive complete flag 0 : no data present in receive buffer register 1 : data present in receive buffer register start reception processing after reading out reception data continued from the previous page checking error uart0 receive buffer register [address 03a7 16 , 03a6 16 ]u0rb uart1 receive buffer register [address 03af 16 , 03ae 16 ]u1rb overrun error flag 0 : no overrun error 1 : overrun error found b7 b0 b7 b0 (b15) (b8) receive data reception enabled uart0 transmit/receive control register 1 [address 03a5 16 ] u0c1 uart1 transmit/receive control register 1 [address 03ad 16 ] u1c1 transmit enable bit 1 : transmission enabled b7 b0 receive enable bit 1 : reception enabled 1 1 uart0 transmit/receive control register 1 [address 03a5 16 ] u0c1 uart1 transmit/receive control register 1 [address 03ad 16 ] u1c1
244 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.4.5 precautions for serial i/o (in clock-synchronous serial i/o) transmission/reception _______ ________ (1) with an external clock selected, and choosing the rts function, the output level of the rtsi pin goes to l when the data-receivable status becomes ready, which informs the transmis- ________ sion side that the reception has become ready. the output level of the rtsi pin goes to h ________ ________ when reception starts. so if the rtsi pin is connected to the ctsi pin on the transmission side, the circuit can transmission and reception data with consistent timing. with the internal _______ clock, the rts function has no effect. figure 2.4.14 shows an example of wiring. figure 2.4.14. example of wiring txd i rxd i clk i cts i txd i rxd i clk i rts i transmitter side ic receiver side ic
245 clock-synchronous serial i/o m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r transmission reception (1) with an external clock selected, perform the following set-up procedure with the clki pin input level = h if the clk polarity select bit = 0 or with the clki pin input level = l if the clk polarity select bit = 1: 1. set the transmit enable bit (to 1) 2. write transmission data to the uarti transmit buffer register ________ _______ 3. l level input to the ctsi pin (when the cts function is selected) (1) in operating the clock-synchronous serial i/o, operating a transmitter generates a shift clock. fix settings for transmission even when using the device only for reception. dummy data is output to the outside from the txdi pin (transmission pin) when receiving data. (2) with the internal clock selected, setting the transmit enable bit to 1 (transmission-enabled status) and setting dummy data in the uarti transmission buffer register generates a shift clock. with the external clock selected, a shift clock is generated when the transmit enable bit is set to 1, dummy data is set in the uarti transmit buffer register, and the external clock is input to the clki pin. (3) in receiving data in succession, an overrun error occurs when the next reception data is made ready in the uarti receive register with the receive complete flag set to 1 (before the content of the uarti receive buffer register is read), and overrun error flag is set to 1. in this instance, the next data is written to the uarti receive buffer register, so handle with this problem by writing programs on transmission side and reception side so that the previous data is transmitted again. if an overrun error occurs, the uarti receive interrupt request bit does not go to 1. (4) to receive data in succession, set dummy data in the lower-order byte of the uarti transmit buffer register every time reception is made. (5) with an external clock selected, perform the following set-up procedure with the clki pin input level = h if the clk polarity select bit = 0 or with the clki pin input level = l if the clk polarity select bit = 1: 1. set receive enable bit (to 1) 2. set transmit enable bit (to 1) 3. write dummy data to the uarti transmit buffer register _______ (6) output from the rts pin goes to l level as soon as the receive enable bit is set to 1. this is not related to the content of the transmit buffer empty flag or the content of the transmit enable bit. _______ output from the rts pin goes to h level when reception starts, and goes to l level when reception is completed. this is not related to the content of the transmit buffer empty flag or the content of the receive complete flag.
246 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.5 clock-asynchronous serial i/o (uart) 2.5.1 overview uart handles communications by means of character-by-character synchronization. the transmission side and the reception side are independent of each other, so full-duplex communication is possible. the following is an overview of the clock-asynchronous serial i/o. (1) transmission/reception format figure 2.5.1 shows the transmission/reception format, and table 2.5.1 shows the names and func- tions of transmission data. figure 2.5.1. transmission/reception format table 2.5.1. transmission data names and functions transfer data length : 7 bits 1st ?7data 1sp 1st ?7data 2sp 1st ?7data ?1par 1sp 1st ?7data ?1par 2sp transfer data length : 8 bits 1st ?8data 1sp 1st ?8data 2sp 1st ?8data ?1par 1sp 1st ?8data ?1par 2sp transfer data length : 9 bits 1st ?9data 1sp 1st ?9data 2sp 1st ?9data ?1par 1sp 1st ?9data ?1par 2sp st : start bit data : character bit (transfer data) par : parity bit sp : stop bit name function st (start bit) data (character bits) sp (stop bit) a 1-bit ??signal to be added immediately before character bits. this bit signals the start of data transmission. transmission data set in the uarti transmit buffer register. a signal to be added immediately after character bits so as to increase data reliability. the level of this signal so varies that the total number of 1's in character bits and this bit always becomes even or odd depending on which parity is chosen, even or odd. par (parity bit) either 1-bit or 2-bit ??signal to be added immediately after character bits (after the parity bit if parity is checked). this / they signals the end of data transmission.
247 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (2) transfer rate the divide-by-16 frequency, resulting from division in the bit rate generator (brg), becomes the trans- fer rate. the count source for the bit rate generator can be selected from f 1 , f 8 , f 32 , and the input from the clk pin. clocks f 1 , f 8 , f 32 are derived by dividing the cpus main clock by 1, 8, and 32 respec- tively. table 2.5.2. example of baud rate setting table 2.5.3. error detection (3) an error detection in clock-asynchronous serial i/o mode, detect errors are shown in table 2.5.3. baud rate (bps) brg's count source system clock : 10mhz system clock : 7.3728mhz brg's set value : n actual time (bps) brg's set value : n 600 1200 2400 4800 9600 14400 19200 28800 31250 f 8 f 8 f 8 f 1 f 1 f 1 f 1 f 1 f 1 129 (81 16 ) 64 (40 16 ) 32 (20 16 ) 129 (81 16 ) 64 (40 16 ) 42 (2a 16 ) 32 (20 16 ) 21 (15 16 ) 19 (13 16 ) 600 1201 2367 4807 9615 14534 18939 28409 31250 95 (5f 16 ) 47 (2f 16 ) 23 (17 16 ) 95 (5f 16 ) 47 (2f 16 ) 31 (1f 16 ) 23 (17 16 ) 15 (f 16 ) 600 1200 2400 4800 9600 14400 19200 28800 actual time (bps) type of error when the flag turns on description how to clear the flag ?this error occurs when the next data lines up before the content of the uarti receive buffer register is read. ?the next data is written to the uarti receive buffer register. ?the uarti receive interrupt request bit does not go to ?? ?this error occurs when the stop bit falls short of the set number of stop bits. ?with parity enabled, this error occurs when the total number of 1's in character bits and the parity bit is different from the specified number. ?this flag turns on when any error (overrun, framing, or parity) is detected. the error is detected when data is transferred from the uarti receive register to the uarti receive buffer register. ?set the serial i/o mode select bits to ?00 2 ? ?set the receive enable bit to ?? ?when all error (overrun, framing, and parity) are removed, the flag is cleared. ?set the serial i/o mode select bits to ?00 2 ? ?set the receive enable bit to ?? ?read the lower-order byte of the uarti receive buffer register. overrun error framing error parity error error-sum flag
248 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (4) how to deal with an error when receiving data, read an error flag and reception data simultaneously to determine which error has occurred. if the data read is erroneous, initialize the error flag and the uarti receive buffer register, then receive the data again. to initialize the uarti receive buffer register 1. set the receive enable bit to 0 (disable reception). 2. set the receive enable bit to 1 again (enable reception). to transmit data again due to an error on the reception side, set the uarti transmit buffer register again, then transmit the data again. to set the uarti transmit buffer register again 1. set the serial i/o mode select bits to 000 2 (invalidate serial i/o). 2. set the serial i/o mode select bits again. 3. set the transmit enable bit to 1 (enable transmission), then set transmission data in the uarti transmit buffer register. (5) functions selection in operating uart, the following functions can be used: _______ _______ (a) cts/rts function _______ cts function is a function in which an external ic can start transmission/reception by means of _______ _______ inputting an l level to the cts pin. the cts pin input level is detected when transmission/reception starts, so if the level is gone to h while transmission/reception is in progress, transmission/recep- tion stops at the next data. _______ _______ rts function is a function to inform an external ic that rts pin output level has changed to l when _______ reception is ready. rts regoes to h at the falling edge of the transfer clock. _______ _______ when using clock-asynchronous serial i/o, choose one of three types of cts/rts functions. _______ _______ ? cts/rts functions disabled _______ _______ cts/rts pin is a programmable i/o port. _______ ? cts function only enabled _______ _______ _______ cts/rts pin performs the cts function. _______ ? rts function only enabled _______ _______ _______ cts/rts pin performs the rts function. (b) sleep mode sleep mode is a mode in which data is transferred to a particular microcomputer among those con- nected by use of clock-asynchronous serial i/o devices. (c) data logic select function this function is to reserve data when writing to transmit buffer register or reading from receive buffer register. the following are examples in which functions (a) to (c) are chosen: _______ ? transmission with: cts function, without: other functions ............................................... p254 _______ ? reception with: rts function, without: other functions .................................................... p258
249 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (6) input to the serial i/o and the direction register to input an external signal to the serial i/o, set the direction register of the relevant port to input. (7) pins related to the serial i/o _________ _________ ? cts 0 , cts 1 pins _______ :input pins for the cts function _________ _________ ? rts 0 , rts 1 pins _______ :output pins for the rts function ? clk 0 , clk 1 pins :input pins for the transfer clock ? rxd 0 , rxd 1 pins :input pins for data ? txd 0 , txd 1 pins :output pins for data/
250 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.5.2. memory map of uarti-related registers (8) registers related to the serial i/o figure 2.5.2 shows the memory map of serial i/o-related registers, and figures 2.5.3 to 2.5.5 show uarti-related registers. uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) uart transmit/receive control register 2 (ucon) 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 0051 16 0052 16 0053 16 0054 16 uart0 transmit interrupt control register (s0tic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control regster(s1tic) uart1 receive interrupt control register(s1ric)
251 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.5.3. uarti-related registers (1) b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmission data symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate uarti bit rate generator b7 b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate function assuming that set value = n, brgi divides the count source by (n + 1) 00 16 to ff 16 values that can be set symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate b7 b0 (b15) (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note: bits 15 through 12 are set to ??when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 and 03a8 16 ) are set to ?00 2 ?or the receive enable bit is set to ?? (bit 15 is set to ??when bits 14 to 12 all are set to ??) bits 14 and 13 are also set to ??when the lower byte of the uarti receive buffer register (addresses 03a6 16 and 03ae 16 ) is read out. invalid invalid invalid oer fer per sum overrun error flag (note) framing error flag (note) parity error flag (note) error sum flag (note) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found reception data w r w r w r reception data nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ??
252 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.5.4. uarti-related registers (2) w r u a r t i t r a n s m i t / r e c e i v e m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t u i m r ( i = 0 , 1 )0 3 a 0 1 6 , 0 3 a 8 1 6 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e b i t s y m b o l m u s t b e f i x e d t o 0 0 1 0 0 0 : s e r i a l i / o i n v a l i d 0 1 0 : i n h i b i t e d 0 1 1 : i n h i b i t e d 1 1 1 : i n h i b i t e d b 2 b 1 b 0 c k d i r s m d 1 s m d 0 s e r i a l i / o m o d e s e l e c t b i t s m d 2 i n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t s t p s p r y p r y e s l e p p a r i t y e n a b l e b i t 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k s t o p b i t l e n g t h s e l e c t b i t o d d / e v e n p a r i t y s e l e c t b i t s l e e p s e l e c t b i t 0 : o n e s t o p b i t 1 : t w o s t o p b i t s 0 : p a r i t y d i s a b l e d 1 : p a r i t y e n a b l e d 0 : s l e e p m o d e d e s e l e c t e d 1 : s l e e p m o d e s e l e c t e d 1 0 0 : t r a n s f e r d a t a 7 b i t s l o n g 1 0 1 : t r a n s f e r d a t a 8 b i t s l o n g 1 1 0 : t r a n s f e r d a t a 9 b i t s l o n g 0 0 0 : s e r i a l i / o i n v a l i d 0 1 0 : i n h i b i t e d 0 1 1 : i n h i b i t e d 1 1 1 : i n h i b i t e d b 2 b 1 b 0 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k i n v a l i d v a l i d w h e n b i t 6 = 1 0 : o d d p a r i t y 1 : e v e n p a r i t y i n v a l i d i n v a l i d m u s t a l w a y s b e 0 f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) u a r t i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 s y m b o la d d r e s sw h e n r e s e t u i c 0 ( i = 0 , 1 )0 3 a 4 1 6 , 0 3 a c 1 6 0 8 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) t x e p t c l k 1 c l k 0 c r s c r d n c h c k p o l b r g c o u n t s o u r c e s e l e c t b i t t r a n s m i t r e g i s t e r e m p t y f l a g 0 : t r a n s m i t d a t a i s o u t p u t a t f a l l i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t r i s i n g e d g e 1 : t r a n s m i t d a t a i s o u t p u t a t r i s i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t f a l l i n g e d g e c l k p o l a r i t y s e l e c t b i t c t s / r t s f u n c t i o n s e l e c t b i t c t s / r t s d i s a b l e b i t d a t a o u t p u t s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 0 : l s b f i r s t 1 : m s b f i r s t 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) 0 : c t s / r t s f u n c t i o n e n a b l e d 1 : c t s / r t s f u n c t i o n d i s a b l e d ( p 4 7 a n d p 7 7 f u n c t i o n a s p r o g r a m m a b l e i / o p o r t ) 0 : t x d i p i n i s c m o s o u t p u t 1 : t x d i p i n i s n - c h a n n e l o p e n - d r a i n o u t p u t u f o r mt r a n s f e r f o r m a t s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 v a l i d w h e n b i t 4 = 0 0 : c t s f u n c t i o n i s s e l e c t e d ( n o t e 1 ) 1 : r t s f u n c t i o n i s s e l e c t e d ( n o t e 2 ) v a l i d w h e n b i t 4 = 0 0 : c t s f u n c t i o n i s s e l e c t e d ( n o t e 1 ) 1 : r t s f u n c t i o n i s s e l e c t e d ( n o t e 2 ) 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) 0 : t x d i p i n i s c m o s o u t p u t 1 : t x d i p i n i s n - c h a n n e l o p e n - d r a i n o u t p u t m u s t a l w a y s b e 0 b i t n a m e b i t s y m b o l m u s t a l w a y s b e 0 n o t e 1 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . n o t e 2 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . 0 : c t s / r t s f u n c t i o n e n a b l e d 1 : c t s / r t s f u n c t i o n d i s a b l e d ( p 4 7 a n d p 7 7 f u n c t i o n a s p r o g r a m m a b l e i / o p o r t ) w r
253 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.5.5. uarti-related registers (3) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register note: when using multiple pins to output the transfer clock, the following requirement must be met: ?uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? u0irs u1irs u0rrm u1rrm invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = ?? 0 : clock output to clk1 1 : clock output to clks1 reserved bit must always be ? must always be ? nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be ?? 0
254 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in transmitting data in uart mode, choose functions from those listed in table 2.5.4. operations of the circled items are described below. figure 2.5.6 shows the operation timing, and figures 2.5.7 and 2.5.8 show the set-up procedures. 2.5.2 operation of serial i/o (transmission in uart mode) table 2.5.4. choosed functions (1) setting the transmit enable bit to 1 and writing transmission data to the uarti transmit buffer register readies the data transmissible status. ________ ________ (2) when input to the ctsi pin goes to l, transmission starts (the ctsi pin needs to be con- trolled on the reception side). (3) transmission data held in the uarti transmit buffer register is transmitted to the uarti transmit register. at this time, the first bit (the start bit) of the transmission data is transmitted from the txdi pin. then, data is transmitted, bit by bit, in sequence: lsb, , msb, parity bit, and stop bit(s). (4) when the stop bit(s) is (are) transmitted, the transmit register empty flag goes to 1, which indicates that transmission is completed. at this time, the uarti transmit interrupt request bit goes to 1. the transfer clock stops at h level. (5) if the transmission condition of the next data is ready when transmission is completed, a start bit is generated following to stop bit(s), and the next data is transmitted. operation item set-up transfer clock source internal clock (f 1 / f 8 / f 32 ) external clock (clki pin) cts function cts function enabled cts function disabled o o transmission interrupt factor transmission buffer empty transmission complete o sleep mode sleep mode off sleep mode selected o
255 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r example of wiring example of operation figure 2.5.6. operation timing of transmission in uart mode t x di ctsi r x d port microcomputer receiver side ic transmit enable bit (te) transmit buffer empty flag (tl) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit txdi ctsi ? ? ? ? ? ? ? ? transmit interrupt request bit (ir) ? ? cleared to ??when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 st shown in ( ) are bit symbols. sp stopped pulsing because transfer enable bit = ? stop bit data is set in uarti transmit buffer register transferred from uarti transmit buffer register to uarti transmit register tc transfer clock when confirming stop bit, stopped transfer clock once because cts = ? started transfer clock again to start transmitting immediately after confirming cts = ? (1) transmission enabled (2) confirme cts (3) start transmission (4) confirme stop bit (5) start transmission the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?cts function is selected. ?transmit interrupt cause select bit = ?? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi
256 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.5.7. set-up procedure of transmission in uart mode (1) continued to the next page setting uarti transmit/receive mode register (i=0, 1) internal/external clock select bit 0 : internal clock stop bit length select bit 0 : one stop bit b7 b0 01 01 0 odd/even parity select bit ( valid when bit 6 = ? ) 0 : odd parity parity enable bit 1 : parity enabled sleep select bit 0 : invalid serial i/o mode select bit 1 0 1 : transfer data 8 bits long b2 b1 b0 0 1 0 uart0 transmit/receive mode register u0mr [address 03a0 16 ] uart1 transmit/receive mode register u1mr [address 03a8 16 ] setting uarti transmit/receive control register 0 (i = 0, 1) uart0 transmit/receive control register 0 u0c0 [address 03a4 16 ] uart1 transmit/receive control register 0 u1c0 [address 03ac 16 ] must be ??in uart mode b7 b0 00 00 brg count source select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 cts/rts function select bit (valid when bit 4 = ?? 0 : cts function is selected data output select bit 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output cts/rts disable bit 0 : cts/rts function enabled transmit register empty flag 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) must be ??in uart mode setting uart transmit/receive control register 2 uart transmit/receive control register 2 ucon [address 03b0 16 ] uart0 transmit interrupt cause select bit 1 : transmission completed (txept = 1) must be ??in uart mode uart1 transmit interrupt cause select bit 1 : transmission completed (txept = 1) invalid in uart mode invalid in uart mode invalid in uart mode reserved bit fix ??to this bit. 00 b7 b0
257 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.5.8. set-up procedure of transmission in uart mode (2) start transmission when ctsi input level = ? setting uarti bit rate generator (i = 0, 1) uarti bit rate generator (i = 0, 1) [address 03a1 16 , 03a9 16 ] uibrg (i = 0, 1) can be set to 00 16 to ff 16 (note) b7 b0 note: write to uarti bit rate generator when transmission/reception is halted. transmission is complete continued from the previous page uart0 transmit/receive control register 1 [address 03a5 16 ] u0c1 uart1 transmit/receive control register 1 [address 03ad 16 ] u1c1 transmit enable bit 1 : transmission enabled b7 b0 1 transmission enabled writing transmit data uart0 transmit buffer register [address 03a3 16 , 03a2 16 ] u0tb uart1 transmit buffer register [address 03ab 16 , 03aa 16 ] u1tb setting transmission data b7 b0 b7 b0 (b15) (b8) uart0 transmit/receive control register 1 [address 03a5 16 ] u0c1 uart1 transmit/receive control register 1 [address 03ad 16 ] u1c1 b7 b0 transmit buffer empty flag 0 : data present in transmit buffer register 1 : no data present in transmit buffer register (writing next transmit data enabled) checking the status of uarti transmit/receive control (i = 0, 1) writing next transmit data uart0 transmit buffer register [address 03a3 16 , 03a2 16 ] u0tb uart1 transmit buffer register [address 03ab 16 , 03aa 16 ] u1tb setting transmission data b7 b0 b7 b0 (b15) (b8)
258 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in receiving data in uart mode, choose functions from those listed in table 2.5.5. operations of the circled items are described below. figure 2.5.9 shows the operation timing, and figures 2.5.10 and 2.5.11 show the set-up procedures. 2.5.3 operation of serial i/o (reception in uart mode) table 2.5.5. choosed functions (1) setting the receive enable bit to 1 readies data-receivable status. at this time, output from ________ the rtsi pin goes to l level to inform the transmission side that the receivable status is ready. (2) when the first bit (the start bit) of reception data is received from the rxdi pin, output from the _______ rts goes to h level. then, data is received, bit by bit, in sequence: lsb, , msb, and stop bit(s). (3) when the stop bit(s) is (are) received, the content of the uarti receive register is transmitted to the uarti receive buffer register. at this time, the receive complete flag goes to 1 to indicate that the reception is completed, _______ the uarti receive interrupt request bit goes to 1, and output from the rts pin goes to l level. (4) the receive complete flag goes to 0 when the lower-order byte of the uarti receive buffer register is read. operation item set-up transfer clock source internal clock (f 1 / f 8 / f 32 ) external clock (clki pin) rts function rts function enabled rts function disabled o o sleep mode sleep mode off sleep mode selected o
259 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r example of wiring example of operation figure 2.5.9. operation timing of reception in uart mode r x di rtsi t x d port microcomputer transmitter side ic clki clk d 0 d 1 d 7 start bit reception started when transfer clock is generated by falling edge of start bit sampled ? receive data taken in brgi's count source receive enable bit rxd i transfer clock receive complete flag rts i stop bit ? ? ? ? ? ? timing of transfer data 8 bits long applies to the following settings : ?ransfer data length is 8 bits. ?arity is disabled. ?ne stop bit ?ts function is selected. receive interrupt request bit ? ? cleared to ??when interrupt request is accepted, or cleared by software transferred from uarti receive register to uarti receive buffer register (1) reception enabled (2) start reception (4) data is read (3) receiving is completed
260 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.5.10. set-up procedure of reception in uart mode (1) continued to the next page uart transmit/receive control register 2 [address 03b0 16 ] ucon invalid in uart mode must be fixed to ??in uart mode invalid in uart mode invalid in uart mode reserved bit fix ??to this bit. b7 b0 00 setting uart transmit/receive control register 2 setting uarti transmit/receive mode register (i=0, 1) internal/external clock select bit 1 : external clock uart0 transmit/receive mode register [address 03a0 16 ] u0mr uart1 transmit/receive mode register [address 03a8 16 ] u1mr valid when bit 6 = ? parity enable bit 0 : parity diabled b7 b0 01 01 1 sleep select bit 0 : sleep mode deselected serial i/o mode select bit 1 0 1 : transfer data 8 bits long b2 b1 b0 00 stop bit length select bit 0 : one stop bit setting uarti transmit/receive control register 0 (i=0, 1) must be fixed to ??in uart mode transmit register empty flag 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) must be fixed to ??in uart mode data output select bit 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uart0 transmit/receive control register 0 [address 03a4 16 ] u0c0 uart1 transmit/receive control register 0 [address 03ac 16 ] u1c0 b7 b0 01 00 brg count source select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 cts/rts function select bit (valid when bit 4 = ?? 1 : rts function is selected cts/rts disable bit 0 : cts/rts function enabled 0
261 uart m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.5.11. set-up procedure of reception in uart mode (2) start reception processing after reading out reception data continued from the previous page checking error uart0 receive buffer register [address 03a7 16 , 03a6 16 ]u0rb uart1 receive buffer register [address 03af 16 , 03ae 16 ]u1rb overrun error flag 0 : no overrun error 1 : overrun error found b7 b0 b7 b0 (b15) (b8) receive data framing error flag 0 : no framing error 1 : framing error found parity error flag 0 : no parity error 1 : parity error found error sum flag 0 : no error 1 : error found setting uarti bit rate generator (i = 0, 1) uarti bit rate generator (i = 0 , 1 ) [address 03a1 16 , 03a9 16 ] uibrg (i = 0, 1) can be set to 00 16 to ff 16 b7 b0 reception enabled uart0 transmit/receive control register 1 [address 03a5 16 ] u0c1 uart1 transmit/receive control register 1 [address 03ad 16 ] u1c1 b7 b0 receive enable bit 1 : reception enabled 1 checking completion of reception uart0 transmit/receive control register 1 [address 03a5 16 ] u0c1 uart1 transmit/receive control register 1 [address 03ad 16 ] u1c1 b7 b0 receive complete flag 0 : no data present in receive buffer register 1 : data present in receive buffer register note: write to uarti bit rate generator when transmission/reception is halted.
262 serial i/o2 2.6 serial i/o2 2.6.1 overview serial i/o2 performs 8-bit data serial communication, synchronized with the clocks. in the automatic transfer serial i/o mode, serial communication of up to 256 bytes can be continuously performed without use of the cpu. the following is the serial i/o2 overview. (1) transfer format transfer format is 8-bit data. (2) transfer rate when selecting an internal clock as the transfer clock, the transfer rate is the division ratio selected by the internal synchronous clock selection bits. any one of f(x in )/4, f(x in )/8, f(x in )/16, f(x in )/32, f(x in )/64, f(x in )/128 or f(x in )/256 can be selected by the internal synchronous clock selection bits. when selecting an external clock as the transfer clock, the transfer rate is the frequency of the clock input to the clk pin. (3) automatic transfer serial i/o mode clock synchronous communication, which does not depend on the cpu, can be continuously per- formed up to 256 bytes. (4) selection function the following selection functions can be applied to serial i/o2. (a) s stb2 output (for selecting internal synchronous clock) ?stb function invalid: s stb2 output pin is used as a programmable i/o pin. ?stb function valid: s stb2 output pin functions as s stb2 or s stb2 output. (b) s busy2 input/output ?s busy2 input/output function invalid: s busy2 pin is used as a programmable i/o pin. ?s busy2 input/output function valid: s busy2 pin functions as input/output of s busy2 or s busy2 . (c) s rdy2 input/output ?s rdy2 input/output function invalid: s rdy2 pin is used as a programmable i/o pin. ?s rdy2 input/output function valid: s rdy2 pin functions as input/output of s rdy2 or s rdy2 . (d) s out2 p-channel output disable (invalid for p9 4 as i/o port) the s out2 output pin can be switched between c-mos 3 state and n-channel open-drain when in the 8-bit or the automatic transfer serial i/o mode. the mode is selected by the serial transfer select bits. (e) lsb first/msb first this function switches the starting bit for the transmission/reception; either bit 0 or bit 7. the following two types can be selected with the transfer direction select bit: ?lsb first: transmission/reception begins with from bit 0. ?msb first: transmission/reception begins with from bit 7.
263 serial i/o2 (f) transfer mode either the full duplex mode or the transmit-only mode can be selected. the s in2 pin can be used as a programmable input/output port in the transmit-only mode. (g) plural transfer clock input/output pin this function switches the pins for transfer clock input/output. by switching the transfer clock pins, data can be transmitted/received to two external ics in a time-sharing manner. (h) s out2 pin control this pin selects either output active (value of last transmitted data or undefined value) or high-imped- ance as the s out2 pin state for non-transfer periods (i.e. before and after serial transfers). (5) input to serial i/o2 and direction register when inputting external signals to serial i/o2, set the corresponding port direction register to input. (6) serial i/o2-related pins (a) s stb2 pin : output pin for stb and stb functions. (b) s busy2 pin : input/output pin for busy and busy functions. (c) s rdy2 pin : input/output pin for rdy and rdy functions. (d) s clk21 , s clk22 pins : input/output pins for transfer clocks. pin is selectable by user. (e) s in2 pin : data input pin. (f) s out2 pin : data output pin.
264 serial i/o2 (7) registers related to serial i/o2 figure 2.6.1 shows the memory map of serial i/o2 related-registers. figures 2.6.2 and 2.6.3 show the serial i/o2 related-registers. 0 3 4 4 1 6 0 3 4 5 1 6 0 3 4 6 1 6 0 3 4 7 1 6 0 3 4 8 1 6 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 ( s i o 2 c o n 2 ) s e r i a l i / o 2 r e g i s t e r / t r a n s f e r c o u n t e r ( s i o 2 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 3 ( s i o 2 c o n 3 ) 0 3 4 3 1 6 0 3 4 2 1 6 0 0 4 f 1 6 0 3 4 0 1 6 s i / o a u t o m a t i c t r a n s f e r i n t e r r u p t c o n t r o l r e g i s t e r ( a s i o i c ) s e r i a l i / o 2 a u t o m a t i c t r a n s f e r d a t a p o i n t e r ( s i o 2 d p ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 ( s i o 2 c o n 1 ) 0 3 4 1 1 6 0 4 0 0 1 6 0 4 f f 1 6 : : a u t o m a t i c t r a n s f e r r a m : : figure 2.6.1. memory map of serial i/o2 related-registers
265 serial i/o2 figure 2.6.2. serial i/o2 related-registers (1) s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 s y m b o la d d r e s sw h e n r e s e t s i o 2 c o n 20 3 4 4 1 6 0 0 1 6 b i t n a m ef u n c t i o n r b i t s y m b o l w b 7b 6b 5b 4 b 3b 2b 1b 0 s r d y 2 s b u s y 2 p i n c o n t r o l b i t s s c o n 2 0 s c o n 2 1 s c o n 2 2 s c o n 2 3 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s y m b o la d d r e s sw h e n r e s e t s i o 2 c o n 10 3 4 2 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l r w b 7b 6b 5b 4b 3b 2b 1b 0 s e r i a l t r a n s f e r s e l e c t b i t s s c o n 1 0 s c o n 1 1 s c o n 1 2 s c o n 1 3 s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t b i t s ( s s t b 2 p i n c o n t r o l b i t ) 0 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) 0 1 : e x t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) 1 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n s s t b 2 o u t p u t . ) 1 1 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n s s t b 2 o u t p u t . ) 0 : s e r i a l i / o i n i t i a l i z a t i o n 1 : s e r i a l i / o e n a b l e d s e r i a l i / o i n i t i a l i z a t i o n b i t t r a n s f e r m o d e s e l e c t b i t 0 : f u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e ( s i n 2 p i n i s a s i n 2 i n p u t . ) 1 : t r a n s m i t - o n l y m o d e ( s i n 2 p i n i s a n i / o p o r t . ) s c o n 1 4 s c o n 1 5 s e r i a l i / o 2 c l o c k p i n s e l e c t b i t t r a n s f e r d i r e c t i o n s e l e c t b i t s c o n 1 6 s c o n 1 7 0 0 : s e r i a l i / o d i s a b l e d ( s e r i a l i / o p i n s a r e i / o p o r t s ) 0 1 : 8 - b i t s s e r i a l i / o 1 0 : i n h i b i t 1 1 : a u t o m a t i c t r a n s f e r s e r i a l i / o ( 8 - b i t s ) 0 : l s b f i r s t 1 : m s b f i r s t 0 : s c l k 2 1 ( s c l k 2 2 p i n i s a n i / o p o r t . ) 1 : s c l k 2 2 ( s c l k 2 1 p i n i s a n i / o p o r t . ) 0 : f u n c t i o n s a s e a c h 1 - b y t e s i g n a l 1 : f u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a s b u s y 2 o u t p u t s s t b 2 o u t p u t f u n c t i o n s e l e c t b i t ( v a l i d i n a u t o m a t i c t r a n s f e r m o d e ) s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g s c o n 2 4 s c o n 2 5 s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t s o u t 2 p i n c o n t r o l b i t ( a t n o - t r a n s f e r s e r i a l d a t a ) s c o n 2 6 s c o n 2 7 0 : o u t p u t a c t i v e 1 : o u t p u t h i g h - i m p e d a n c e 0 : c m o s 3 - s t a t e ( p - c h a n n e l o u t p u t i s v a l i d . ) 1 : n - c h a n n e l o p e n - d r a i n ( p - c h a n n e l o u t p u t i s i n v a l i d . ) b 3 b 2 b 1 b 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 s r d y 2 p i ns b u s y 2 p i n i / o p o r ti / o p o r t n o t u s e d s r d y 2 o u t p u ti / o p o r t s r d y 2 o u t p u ti / o p o r t i / o p o r ts b u s y 2 i n p u t i / o p o r ts b u s y 2 i n p u t i / o p o r ts b u s y 2 o u t p u t i / o p o r ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t b 1 b 0 b 3 b 2
266 serial i/o2 serial i/o2 control register 3 symbol address when reset sio2con3 0348 16 00000000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 automatic transfer interval set bits ttran0 ttran1 ttran2 ttran3 internal synchronous clock selection bits 000:f(x in )/4 001:f(x in )/8 010:f(x in )/16 011:f(x in )/32 100:f(x in )/64 101:f(x in )/128 110:f(x in )/256 ttran4 tclk0 tclk1 tclk2 00000 :2 cycles of transfer clocks 00001 :3 cycles of transfer clocks : 11110 :32 cycles of transfer clocks 11111 :33 cycles of transfer clocks data is written to a latch and read from a decrement counter. b4b3b2b1b0 b7b6b5 serial i/o2 automatic transfer data pointer symbol address when reset sio2dp 0340 16 00 16 function r w b7 b6 b5 b4 b3 b2 b1 b0 ?automatic transfer data pointer set specify the low-order 8 bits of the first data store address on the serial i/o automatic transfer ram. data is written into the latch and read from the decrement counter. serial i/o2 register/transfer counter symbol address when reset sio2 0346 16 00 16 function r w b7 b6 b5 b4 b3 b2 b1 b0 ?number of automatic transfer data set set the number of automatic transfer data. set a value one less than number of transfer data. data is written into the latch and read from the decrement counter. figure 2.6.3. serial i/o2 related-registers (2)
267 serial i/o2 2.6.2 serial i/o2 connection examples (1) control of peripheral ic equipped with cs pin figure 2.6.4 shows connection examples with peripheral ics which have the cs pin. the automatic transfer function can be used in all examples. s b u s y 2 s c l k 2 1 s o u t 2 s i n 2 c s c l k i n o u t s b u s y 2 s c l k 2 1 s o u t 2 c s c l k d a t a ( 1 ) o n l y t r a n s m i s s i o n ( u s i n g s i n 2 p i n a s i / o p o r t ) s b u s y 2 s c l k 2 1 s o u t 2 s i n 2 c s c l k i n o u t p o r t s c l k 2 1 s o u t 2 s i n 2 p o r t c s c l k i n o u t c s c l k i n o u t m 3 0 2 1 8 g r o u p p e r i p h e r a l i c ( o s d c o n t r o l l e r , e t c . ) ( 2 ) t r a n s m i s s i o n a n d r e c e p t i o n m 3 0 2 1 8 g r o u pp e r i p h e r a l i c ( e e p r o m , e t c . ) ( 3 ) t r a n s m i s s i o n a n d r e c e p t i o n ( w h e n c o n n e c t i n g s i n 2 w i t h s o u t 2 ) ( w h e n c o n n e c t i n g i n w i t h o u t i n p e r i p h e r a l i c ) m 3 0 2 1 8 g r o u p ] 1 p e r i p h e r a l i c ] 2 ( e e p r o m , e t c . ) ( 4 ) c o n n e c t i o n o f p l u r a l i c m 3 0 2 1 8 g r o u p p e r i p h e r a l i c 1 p e r i p h e r a l i c 2 ] 1 : s e l e c t a n n - c h a n n e l o p e n - d r a i n o u t p u t f o r s o u t 2 p i n o u t p u t c o n t r o l . ] 2 : u s e t h e o u t p i n o f p e r i p h e r a l i c w h i c h i s a n n - c h a n n e l o p e n - d r a i n o u t p u t a n d b e c o m e s h i g h i m p e - d a n c e d u r i n g r e c e i v i n g d a t a . n o t e : p o r t m e a n s a n o u t p u t p o r t c o n t r o l l e d b y s o f t w a r e . figure 2.6.4. serial i/o2 onnection examples (1)
268 serial i/o2 (2) mcu connections figure 2.6.5 shows connection examples with other mcus. s c l k 2 1 s o u t 2 s i n 2 s c l k 2 2 p o r t c l k i n o u t ( 4 ) u s i n g s w i t c h f u n c t i o n o f c l k s i g n a l o u t p u t p i n s , s c l k 2 2 ( s e l e c t i n g i n t e r n a l c l o c k ) c l k i n o u t c s s c l k 2 1 s o u t 2 s i n 2 c l k i n o u t s c l k 2 1 s o u t 2 s i n 2 c l k i n o u t s r d y 2 s c l k 2 1 s o u t 2 s i n 2 r d y c l k i n o u t ( 1 ) s e l e c t i n g i n t e r n a l c l o c k m 3 0 2 1 8 g r o u pm i c r o c o m p u t e r ( 2 ) s e l e c t i n g e x t e r n a l c l o c k ( 3 ) u s i n g s r d y 2 s i g n a l o u t p u t f u n c t i o n ( s e l e c t i n g e x t e r n a l c l o c k ) p e r i p h e r a l i c m 3 0 2 1 8 g r o u pm i c r o c o m p u t e r m 3 0 2 1 8 g r o u pm i c r o c o m p u t e r m i c r o c o m p u t e r m 3 0 2 1 8 g r o u p figure 2.6.5. serial i/o2 onnection examples (2)
269 serial i/o2 2.6.3 serial i/o2 modes figure 2.6.6 shows serial i/o2 modes. s e r i a l i / o 2 8 - b i t s e r i a l i / o a u t o m a t i c t r a n s f e r s e r i a l i / o i n t e r n a l c l o c k u s i n g h a n d s h a k e s i g n a l e x t e r n a l c l o c k o u t p u t s r d y 2 ] s i g n a l f u l l d u p l e x m o d e t r a n s m i t - o n l y m o d e n o t u s i n g h a n d s h a k e s i g n a l u s i n g h a n d s h a k e s i g n a l n o t u s i n g h a n d s h a k e s i g n a l i np u t s r d y 2 ] s i g n a l ( n o t e ) o u t p u t s b u s y2 ] s i g n a l i np u t s b u s y2 ] s i g n a l o u t p u t s s t b2 ] s i g n a l o u t p u t s r d y 2 ] s i g n a l i np u t s r d y 2 ] s i g n a l ( n o t e ) o u t p u t s b u s y2 ] s i g n a l i np u t s b u s y2 ] s i g n a l n o t e : t h i s i s o n l y v a l i d w h e n o u t p u t t i n g t h e s b u s y 2 s i g n a l . ] a c t i v e l o g i c c a n a p p l y t o e a c h s i g n a l o f s r d y 2 , s b u s y 2 , s s t b 2 . figure 2.6.6. serial i/o2 modes
270 serial i/o2 2.6.4 serial i/o2 operations (transmission in 8-bit serial i/o mode) the functions listed in table 2.6.1 can be selected in the 8-bit serial i/o mode for serial i/o2 transmission/ reception. operations of the circled items are described below. figure 2.6.7 shows the operation timing, and figures 2.6.8 and 2.6.9 show the set-up procedure. operation (1) serial i/o2 becomes transmission-enabled with the following settings: serial transfer select bits scon10 to 1 and scon11 to 0; transfer mode select bit (scon15) to 1; serial i/o initialization bit (scon14) to 1. (2) when transmission data is written to the serial i/o2 register, transmission starts and the serial transfer status flag is set to 1. (3) the transmission data is transmitted bit by bit from the lower bits, synchronized with each falling edge. (4) when one-byte data transmission is completed, the serial transfer status flag is set to 0 to indicate the transmission completion. the transfer clock stops at h level. (5) continuous transmission can be performed by setting the next transmission data in the serial i/o2 register during transmission, before output of the 8th bit. i t e m s e t - u ps e t - u p o i t e m t r a n s f e r c l o c k s o u r c e i n t e r n a l c l o c k ( f 1 / f 8 / f 3 2 ) a u t o m a t i c t r a n s f e r s e r i a l i / o s e l e c t e d o o s s t b 2 o u t p u t f u n c t i o n o o t r a n s f e r d i r e c t i o n e xt e r n a l c l o c k ( c l k i p i n ) n o t s e l e c t e d n o t s e l e c t e d s s t b 2 ( h a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d ) s s t b 2 ( l a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d ) l s b f i r s t o ms b f i r s t s b u s y2 f u n c t i o n n o t s e l e c t e d s b u s y 2 i n p u t s b u s y2 o u t p u t ( h a t s t o p r e q u i r e d ) s b u s y2 o u t p u t ( l a t s t o p r e q u i r e d ) s r d y2 f u n c t i o n n o t s e l e c t e d s r d y 2 i n p u t s r d y 2 o u t p u t s r d y2 o u t p u t ( h a t r e a d y ) s r d y2 o u t p u t ( l a t r e a d y ) table 2.6.1. selectable functions
271 serial i/o2 figure 2.6.7. operation timing of transmission in 8-bit serial i/o mode, using plural transfer clock output function output s b u s y 2 s c l k 2 1 s o u t 2 c s c l k d a t a ? ? ? ? d 0 t c d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s o u t 2 ( 2 ) t r a n s m i s s i o n s t a r t( 4 ) t r a n s m i s s i o n i s c o m p l e t e d m 3 0 2 1 8 g r o u pp e r i p h e r a l i c c o n n e c t i o n e x a m p l e o p e r a t i o n e x a m p l e i n t e r n a l c l o c k s e r i a l t r a n s f e r s t a t u s f l a g ( b i t 5 o f a d d r e s s 0 3 4 4 1 6 ) s b u s y 2 ( o u t p u t ) s c l k 2 1 ( o u t p u t ) t c : i n t e r n a l s y n c h r o n o u s c l o c k w h i c h i s s e l e c t e d w i t h b i t s 5 t o 7 o f a d d r e s s 0 3 4 8 1 6 t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : i n t e r n a l c l o c k i s s e l e c t e d 8 - b i t s e r i a l i / o m o d e s b u s y 2 o u t p u t t i m i n g : e a c h 1 b y t e
272 serial i/o2 figure 2.6.8. set-up procedure for transmission in 8-bit serial i/o mode, using plural transfer clock output function output (1) 0 0 1 0 0 0 0 0 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s e t - u p c o n t i n u e d t o t h e n e x t p a g e s e r i a l t r a n s f e r s e l e c t b i t s b 1 b 0 0 0 : s e r i a l i / o d i s a b l e d ( s e r i a l i / o p i n s a r e i / o p o r t s ) s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t b i t s b 3 b 2 0 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) s e r i a l i / o i n i t i a l i z a t i o n b i t 0 : s e r i a l i / o i n i t i a l i z a t i o n t r a n s f e r m o d e s e l e c t b i t 1 : t r a n s m i t - o n l y m o d e ( s i n 2 p i n i s a n i / o p o r t . ) t r a n s f e r d i r e c t i o n s e l e c t b i t 0 : l s b f i r s t s e r i a l i / o 2 c l o c k p i n s e l e c t b i t 0 : s c l k 2 1 ( s c l k 2 2 p i n i s a n i / o p o r t . ) 0 0 0 1 1 0 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 [ a d d r e s s 0 3 4 4 1 6 ] s i o 2 c o n 2 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 s e t - u p s r d y 2 s b u s y 2 p i n c o n t r o l b i t s b 3 b 2 b 1 b 0 0 1 1 0 : s r d y 2 p i n a s i / o p o r t , s b u s y2 p i n a s s b u s y 2 o u t p u t s b u s y 2 o u t p u t s s t b 2 o u t p u t f u n c t i o n s e l e c t b i t 0 : f u n c t i o n s a s e a c h 1 - b y t e s i g n a l s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g s o u t 2 p i n c o n t r o l b i t 0 : o u t p u t a c t i v e s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s 3 - s t a t e ( p - c h a n n e l o u t p u t i s v a l i d . ) 0 0 1 1 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 3 [ a d d r e s s 0 3 4 8 1 6 ] s i o 2 c o n 3 s e r i a l i / o 2 c o n t r o l r e g i s t e r 3 s e t - u p a u t o m a t i c t r a n s f e r i n t e r v a l s e t b i t s b 4 b 3 b 2 b 1 b 0 0 0 0 0 0 : 2 c y c l e s o f t r a n s f e r c l o c k s 0 0 0 0 1 : 3 c y c l e s o f t r a n s f e r c l o c k s : 1 1 1 1 0 : 3 2 c y c l e s o f t r a n s f e r c l o c k s 1 1 1 1 1 : 3 3 c y c l e s o f t r a n s f e r c l o c k s i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b 7 b 6 b 5 0 1 1 : f ( x i n ) / 3 2 0 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s e t - u p s e r i a l t r a n s f e r s e l e c t b i t s b 1 b 0 0 1 : 8 - b i t s e r i a l i / o d i s a b l e d
273 serial i/o2 figure 2.6.9. set-up procedure for transmission in 8-bit serial i/o mode, using plural transfer clock output function output (2) b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 e n a b l i n g tr a n s m i s s i o n t r a n s m i s s i o n i s c o m p l e t e d s e r i a l i / o i n i t i a l i z a t i o n b i t ( n o t e ) 1 : s e r i a l i / o e n a b l e d b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 [ a d d r e s s 0 3 4 4 1 6 ] s i o 2 c o n 2 c o n f i r m a t i o n o f c o m p l e t e t r a n s m i s s i o n s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g 1 n o t e : a f t e r s e t t i n g t h e s e r i a l t r a n s f e r s e l e c t b i t s , p e r f o r m t h i s s e t - u p . b 7b 0 s e r i a l i / o 2 r e g i s t e r [ a d d r e s s 0 3 4 6 1 6 ] s i o 2 w r i t i n g t r a n s m i s s i o n d a t a s e t t r a n s m i s s i o n d a t a f r o m t h e p r e v i o u s p a g e
274 serial i/o2 2.6.5 serial i/o2 operations (transmission/reception in automatic transfer serial i/o mode) the functions listed in table 2.6.2 can be selected in the automatic transfer serial i/o mode for serial i/o2 transmission/reception. operations of the circled items are described below. figure 2.6.10 shows the operation timing, and figures 2.6.11 and 2.6.12 show the set-up procedure. operation (1) after setting the relevant registers, by writing the transfer byte number to the serial i/o2 transfer counter, the serial transfer status flag is set to 1 and automatic transfer starts. (2) the transmission data is transmitted bit by bit from the lower bits, synchronized with each falling edge. the reception data is received bit by bit from the upper bits, synchronized with each rising edge. (3) when eight-byte data transmission/reception is completed, the serial transfer status flag is set to 0 to indicate the transmission/reception completion. the transfer clock stops at h level. table 2.6.2. selectable functions i t e m s e t - u ps e t - u p o i t e m t r a n s f e r c l o c k s o u r c e i n t e r n a l c l o c k ( f 1 / f 8 / f 3 2 ) a u t o m a t i c t r a n s f e r s e r i a l i / o s e l e c t e d o o s s t b 2 o u t p u t f u n c t i o n o o t r a n s f e r d i r e c t i o n e xt e r n a l c l o c k ( c l k i p i n ) n o t s e l e c t e d n o t s e l e c t e d s s t b 2 ( h a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d ) s s t b 2 ( l a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d ) l s b f i r s t o ms b f i r s t s b u s y2 f u n c t i o n n o t s e l e c t e d s b u s y 2 i n p u t s b u s y2 o u t p u t ( h a t s t o p r e q u i r e d ) s b u s y2 o u t p u t ( l a t s t o p r e q u i r e d ) s r d y2 f u n c t i o n n o t s e l e c t e d s r d y 2 i n p u t s r d y 2 o u t p u t s r d y2 o u t p u t ( h a t r e a d y ) s r d y2 o u t p u t ( l a t r e a d y )
275 serial i/o2 figure 2.6.10. operation timing of transmission/reception in automatic transfer serial i/o mode s c l k 2 1 s o u t 2 s i n 2 c l k s i n s o u t m 3 0 2 1 8 g r o u pp e r i p h e r a l i c t c s c l k 2 1 s i n 2 s o u t 2 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ( 1 ) t r a n s m i s s i o n / r e c e p t i o n s t a r t ( 3 ) t r a n s m i s s i o n / r e c e p t i o n i s c o m p l e t e d s e r i a l t r a n s f e r s t a t u s f l a g ( b i t 5 o f a d d r e s s 0 3 4 4 1 6 ) t c : i n t e r n a l s y n c h r o n o u s c l o c k w h i c h i s s e l e c t e d w i t h b i t s 5 t o 7 o f a d d r e s s 0 3 4 8 1 6 t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : i n t e r n a l c l o c k i s s e l e c t e d a u t o m a t i c t r a n s f e r s e r i a l i / o m o d e t r a n s f e r c l o c k 0 w r i t i n g t o s e r i a l i / o 2 t r a n s f e r c o u n t e r ( a d d r e s s 0 3 4 6 1 6 ) 1 0 s e r i a l i / o 2 i n t e r r u p t r e q u e s t t r a n s f e r i n t e r v a lt r a n s f e r i n t e r v a l t r a n s m i s s i o n / r e c e p t i o n o f t h e s e c o n d b y t e t r a n s m i s s i o n / r e c e p t i o n o f t h e e i g h t h b y t e c l e a r e d t o 0 w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y s o f t w a r e connection example operation example
276 serial i/o2 figure 2.6.11. set-up procedure for transmission/reception in automatic transfer serial i/o mode (1) 0 0 0 0 0 0 0 0 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s e t - u p c o n t i n u e d t o t h e n e x t p a g e s e r i a l t r a n s f e r s e l e c t b i t s b 1 b 0 0 0 : s e r i a l i / o d i s a b l e d ( s e r i a l i / o p i n s a r e i / o p o r t s ) s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t b i t s b 3 b 2 0 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) s e r i a l i / o i n i t i a l i z a t i o n b i t 0 : s e r i a l i / o i n i t i a l i z a t i o n t r a n s f e r m o d e s e l e c t b i t 0 : f u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e ( s i n 2 p i n i s a s i n 2 i n p u t . ) t r a n s f e r d i r e c t i o n s e l e c t b i t 0 : l s b f i r s t s e r i a l i / o 2 c l o c k p i n s e l e c t b i t 0 : s c l k 2 1 ( s c l k 2 2 p i n i s a n i / o p o r t . ) 0 0 0 0 0 0 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 [ a d d r e s s 0 3 4 4 1 6 ] s i o 2 c o n 2 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 s e t - u p s r d y 2 s b u s y 2 p i n c o n t r o l b i t s b 3 b 2 b 1 b 0 0 0 0 0 : s r d y 2 p i n a n d s b u s y2 p i n a s i / o p o r t s b u s y 2 o u t p u t s s t b 2 o u t p u t f u n c t i o n s e l e c t b i t 0 : f u n c t i o n s a s e a c h 1 - b y t e s i g n a l 1 : f u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g s o u t 2 p i n c o n t r o l b i t 0 : o u t p u t a c t i v e s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s 3 - s t a t e ( p - c h a n n e l o u t p u t i s v a l i d . ) 0 1 1 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 3 [ a d d r e s s 0 3 4 8 1 6 ] s i o 2 c o n 3 s e r i a l i / o 2 c o n t r o l r e g i s t e r 3 s e t - u p a u t o m a t i c t r a n s f e r i n t e r v a l s e t b i t s b 4 b 3 b 2 b 1 b 0 0 0 0 0 0 : 2 c y c l e s o f t r a n s f e r c l o c k s i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b 7 b 6 b 5 0 1 1 : f ( x i n ) / 3 2 1 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s e t - u p s e r i a l t r a n s f e r s e l e c t b i t s b 1 b 0 1 1 : a u t o m a t i c t r a n s f e r s e r i a l i / o ( 8 - b i t ) 00000
277 serial i/o2 figure 2.6.12. set-up procedure for transmission/reception in automatic transfer serial i/o mode (2) b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 e n a b l i n g tr a n s m i s s i o n t r a n s m i s s i o n / r e c e p t i o n i s c o m p l e t e d s e r i a l i / o i n i t i a l i z a t i o n b i t 1 : s e r i a l i / o e n a b l e d b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 [ a d d r e s s 0 3 4 4 1 6 ] s i o 2 c o n 2 c o n f i r m a t i o n o f c o m p l e t e a u t o m a t i c t r a n s m i s s i o n s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g 1 b 7b 0 a u t o m a t i c t r a n s f e r r a m [ a d d r e s s e s 0 4 0 0 1 6 t o 0 4 f f 1 6 ] w r i t i n g t r a n s m i s s i o n d a t a s e t t r a n s m i s s i o n d a t a f o r t r a n s m i s s i o n b y t e n u m b e r ( 8 b y t e s ) t o a d d r e s s e s 0 4 0 0 1 6 t o 0 4 0 7 1 6 . t h e a r e a f r o m a d d r e s s e s 0 4 0 8 1 6 t o 0 4 f f 1 6 , w h i c h i s n o t u s e d i n t h i s e x a m p l e , c a n b e u s e d a s g e n e r a l - p u r p o s e r a m . b 7b 0 s e r i a l i / o 2 a u t o m a t i c t r a n s f e r d a t a p o i n t e r [ a d d r e s s 0 3 4 0 1 6 ] s i o 2 d p s e r i a l i / o 2 a u t o m a t i c t r a n s f e r d a t a p o i n t e r s e t t h e l o w e r 8 b i t s ( 0 7 1 6 ) o f a d d r e s s 0 4 0 7 1 6 ( n o t e ) n o t e : s p e c i f y t h e l o w e r 8 b i t s o f t h e f i r s t d a t a s t o r e a d d r e s s o n t h e s e r i a l i / o a u t o m a t i c t r a n s f e r r a m . w h e n s e t t i n g a v a l u e , w r i t e a t n o n - t r a n s m i s s i o n / r e c e p t i o n . f r o m t h e p r e v i o u s p a g e 1 1 1 0 0 0 0 0 b 7b 0 s e r i a l i / o 2 t r a n s f e r c o u n t e r [ a d d r e s s 0 3 4 6 1 6 ] s i o 2 a u t o m a t i c t r a n s f e r s t a r t s e t 7 = ( t r a n s f e r b y t e n u m b e r 1 ) w r i t i n g t o t h i s r e g i s t e r s t a r t s a u t o m a t i c t r a n s f e r . o t h e r p r o c e s s e s c a n b e p e r f o r m e d w h i l e a u t o m a t i c t r a n s f e r i s b e i n g p e r f o r m e d . b 7b 0 a u t o m a t i c t r a n s f e r r a m [ a d d r e s s e s 0 4 0 0 1 6 t o 0 4 f f 1 6 ] t a k i n g i n r e c e p t i o n d a t a t a k e i n r e c e p t i o n d a t a a t a d d r e s s e s 0 4 0 0 1 6 t o 0 4 0 7 1 6 i n t o t h e r a m f o r p r o c e s s .
278 serial i/o2 2.6.6 serial i/o2 operations (transmission/reception in automatic transfer serial i/o mode, using handshake signal) the functions listed in table 2.6.3 can be selected in the automatic transfer serial i/o mode for serial i/o2 transmission/reception. operations of the circled items are described below. figure 2.6.13 shows the operation timing, and figures 2.6.14 and 2.6.15 show the set-up procedure. operation (1) after setting the relevant registers, by writing the transfer byte number to the serial i/o2 transfer counter, the serial transfer status flag is set to 1 and automatic transfer starts. s rdy2 output simultaneously goes to h level. (2) when l level is input to the s busy2 pin, the s rdy2 output goes to l level, synchronized with the falling edge of the transfer clock, and the serial transfer starts. (3) the transmission data is transmitted bit by bit from the lower bits, synchronized with each falling edge. the reception data is received bit by bit from the upper bits, synchronized with each rising edge. (4) when sixteen-byte data transmission/reception is completed, the serial transfer status flag is set to 0 to indicate the transmission/reception completion. the transfer clock stops at h level. table 2.6.3. selectable functions i t e m s e t - u ps e t - u p o i t e m t r a n s f e r c l o c k s o u r c e i n t e r n a l c l o c k ( f 1 / f 8 / f 3 2 ) a u t o m a t i c t r a n s f e r s e r i a l i / o s e l e c t e d o o s s t b 2 o u t p u t f u n c t i o n o o t r a n s f e r d i r e c t i o n e xt e r n a l c l o c k ( c l k i p i n ) n o t s e l e c t e d n o t s e l e c t e d s s t b 2 ( h a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d ) s s t b 2 ( l a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d ) l s b f i r s t o ms b f i r s t s b u s y2 f u n c t i o n n o t s e l e c t e d s b u s y 2 i n p u t s b u s y2 o u t p u t ( h a t s t o p r e q u i r e d ) s b u s y2 o u t p u t ( l a t s t o p r e q u i r e d ) s r d y2 f u n c t i o n n o t s e l e c t e d s r d y 2 i n p u t s r d y 2 o u t p u t s r d y2 o u t p u t ( h a t r e a d y ) s r d y2 o u t p u t ( l a t r e a d y )
279 serial i/o2 figure 2.6.13. operation timing of transmission/reception in automatic transfer serial i/o mode connection example operation example c l k 2 1 s o u t 2 s i n 2 c l k i n o u t s r d y 2 r d y s b u s y 2 b u s y m 3 0 2 1 8 g r o u pp e r i p h e r a l i c s c l k 2 1 s i n 2 s o u t 2 s r d y 2 s b u s y 2 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t c ( 2 ) t r a n s m i s s i o n / r e c e p t i o n s t a r t ( 4 ) t r a n s m i s s i o n / r e c e p t i o n i s c o m p l e t e d s e r i a l t r a n s f e r s t a t u s f l a g ( b i t 5 o f a d d r e s s 0 3 4 4 1 6 ) t c : i n t e r n a l s y n c h r o n o u s c l o c k w h i c h i s s e l e c t e d w i t h b i t s 5 t o 7 o f a d d r e s s 0 3 4 8 1 6 t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : i n t e r n a l c l o c k i s s e l e c t e d a u t o m a t i c t r a n s f e r s e r i a l i / o m o d e t r a n s f e r c l o c k w r i t i n g t o s e r i a l i / o 2 t r a n s f e r c o u n t e r ( a d d r e s s 0 3 4 6 1 6 ) s e r i a l i / o 2 i n t e r r u p t r e q u e s t t r a n s f e r i n t e r v a lt r a n s f e r i n t e r v a l t r a n s m i s s i o n / r e c e p t i o n o f t h e s e c o n d b y t e t r a n s m i s s i o n / r e c e p t i o n o f t h e s i x t e e n t h b y t e c l e a r e d t o 0 w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y s o f t w a r e ( 1 ) a u t o m a t i c t r a n s f e r s t a r t 1 0 1 0
280 serial i/o2 figure 2.6.14. set-up procedure for transmission/reception in automatic transfer serial i/o mode (1) 0 0 0 0 0 0 0 0 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s e t - u p c o n t i n u e d t o t h e n e x t p a g e s e r i a l t r a n s f e r s e l e c t b i t s b 1 b 0 0 0 : s e r i a l i / o d i s a b l e d ( s e r i a l i / o p i n s a r e i / o p o r t s ) s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t b i t s b 3 b 2 0 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) s e r i a l i / o i n i t i a l i z a t i o n b i t 0 : s e r i a l i / o i n i t i a l i z a t i o n t r a n s f e r m o d e s e l e c t b i t 0 : f u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e ( s i n 2 p i n i s a s i n 2 i n p u t . ) t r a n s f e r d i r e c t i o n s e l e c t b i t 0 : l s b f i r s t s e r i a l i / o 2 c l o c k p i n s e l e c t b i t 0 : s c l k 2 1 ( s c l k 2 2 p i n i s a n i / o p o r t . ) 0 0 1 1 1 1 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 [ a d d r e s s 0 3 4 4 1 6 ] s i o 2 c o n 2 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 s e t - u p s r d y 2 s b u s y 2 p i n c o n t r o l b i t s b 3 b 2 b 1 b 0 1 1 1 1 : s r d y 2 p i n a s s r d y 2 o u t p u t , s b u s y2 p i n a s s b u s y 2 i n p u t s b u s y 2 o u t p u t s s t b 2 o u t p u t f u n c t i o n s e l e c t b i t 1 : f u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g s o u t 2 p i n c o n t r o l b i t 0 : o u t p u t a c t i v e s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s 3 - s t a t e ( p - c h a n n e l o u t p u t i s v a l i d . ) 0 1 1 b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 3 [ a d d r e s s 0 3 4 8 1 6 ] s i o 2 c o n 3 s e r i a l i / o 2 c o n t r o l r e g i s t e r 3 s e t - u p a u t o m a t i c t r a n s f e r i n t e r v a l s e t b i t s b 4 b 3 b 2 b 1 b 0 0 0 0 0 0 : 2 c y c l e s o f t r a n s f e r c l o c k s i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b 7 b 6 b 5 0 1 1 : f ( x i n ) / 3 2 1 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s e t - u p s e r i a l t r a n s f e r s e l e c t b i t s b 1 b 0 1 1 : a u t o m a t i c t r a n s f e r s e r i a l i / o ( 8 - b i t ) 00000 1
281 serial i/o2 figure 2.6.15. set-up procedure for transmission/reception in automatic transfer serial i/o mode (2) b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 [ a d d r e s s 0 3 4 2 1 6 ] s i o 2 c o n 1 e n a b l i n g tr a n s m i s s i o n t r a n s m i s s i o n / r e c e p t i o n i s c o m p l e t e d s e r i a l i / o i n i t i a l i z a t i o n b i t 1 : s e r i a l i / o e n a b l e d b 7b 0 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 [ a d d r e s s 0 3 4 4 1 6 ] s i o 2 c o n 2 c o n f i r m a t i o n o f c o m p l e t e a u t o m a t i c t r a n s m i s s i o n s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g 1 b 7b 0 a u t o m a t i c t r a n s f e r r a m [ a d d r e s s e s 0 4 0 0 1 6 t o 0 4 f f 1 6 ] w r i t i n g t r a n s m i s s i o n d a t a s e t t r a n s m i s s i o n d a t a f o r t r a n s m i s s i o n b y t e n u m b e r ( 1 6 b y t e s ) t o a d d r e s s e s 0 4 0 0 1 6 t o 0 4 0 f 1 6 . t h e a r e a f r o m a d d r e s s e s 0 4 1 0 1 6 t o 0 4 f f 1 6 , w h i c h i s n o t u s e d i n t h i s e x a m p l e , c a n b e u s e d a s g e n e r a l - p u r p o s e r a m . b 7b 0 s e r i a l i / o 2 a u t o m a t i c t r a n s f e r d a t a p o i n t e r [ a d d r e s s 0 3 4 0 1 6 ] s i o 2 d p s e r i a l i / o 2 a u t o m a t i c t r a n s f e r d a t a p o i n t e r s e t 0 f 1 6 ( n o t e ) n o t e : s p e c i f y t h e l o w e r 8 b i t s o f t h e f i r s t d a t a s t o r e a d d r e s s o n t h e s e r i a l i / o a u t o m a t i c t r a n s f e r r a m . w h e n s e t t i n g a v a l u e , w r i t e a t n o n - t r a n s m i s s i o n / r e c e p t i o n . f r o m t h e p r e v i o u s p a g e 1 1 1 1 0 0 0 0 b 7b 0 s e r i a l i / o 2 t r a n s f e r c o u n t e r [ a d d r e s s 0 3 4 6 1 6 ] s i o 2 a u t o m a t i c t r a n s f e r s t a r t s e t 1 5 = ( t r a n s f e r b y t e n u m b e r 1 ) w r i t i n g t o t h i s r e g i s t e r s t a r t s a u t o m a t i c t r a n s f e r . o t h e r p r o c e s s e s c a n b e p e r f o r m e d w h i l e a u t o m a t i c t r a n s f e r i s b e i n g p e r f o r m e d . b 7b 0 a u t o m a t i c t r a n s f e r r a m [ a d d r e s s e s 0 4 0 0 1 6 t o 0 4 f f 1 6 ] t a k i n g i n r e c e p t i o n d a t a t a k e i n r e c e p t i o n d a t a a t a d d r e s s e s 0 4 0 0 1 6 t o 0 4 0 f 1 6 i n t o t h e r a m f o r p r o c e s s .
282 serial i/o2 2.6.7 precautions for serial i/o2 (1) clock (a) using internal clock after setting the synchronous clock to an internal clock, clear the serial i/o interrupt request bit before performing a normal serial i/o transfer or a serial i/o automatic transfer. (b) using external clock after inputting h level to the external clock input pin, clear the serial i/o interrupt request bit before performing a normal serial i/o transfer or a serial i/o automatic transfer. (2) using serial i/o2 interrupt clear bit 3 of the interrupt control register to 0 by software before enabling interrupts. (3) state of s out2 pin the s out2 pin control bit of the serial i/o2 control register 2 can be used to select the s out2 pin state for non-transfer periods. either output active or high-impedance can be selected. however, when using an external synchronous clock, set the s out2 pin control bit to 1 while the serial i/o2 clock input is in h level (after transfer completion) in order to put the s out2 pin in the high-impedance state. (4) serial i/o initialization bit ?to terminate a serial transfer while transferring, set 0 to the serial i/o initialization bit of the serial i/o2 control register 1. ?when 1 is written to the serial i/o initialization bit, serial i/o2 is enabled, however, each register is not initialized. the value of each register needs to be set by software. (5) handshake signal (a) s busy2 input signal input h level to the s busy2 input and l level to the s busy2 input in the initial state. when using the external synchronous clock, switch the input level to the s busy2 input and the s busy2 input while the serial i/o2 clock input is in h level. (b) s rdy2 input/output signal when using the internal synchronous clock, input l level to the s rdy2 input and h level to the s rdy2 input in the initial state. (6) in 8-bit serial i/o mode when the external synchronous clock is used, the contents of the serial i/o2 register are being shifted continually while the transfer clock is input to the serial i/o2 clock pin. at this time, the clock must be controlled externally.
283 serial i/o2 (7) in automatic transfer serial i/o mode (a) when using ?s busy2 output and, ?s busy2 output?s stb2 output function as signals for each transfer data, which is set by s busy2 output?s stb2 output function select bit of the serial i/o2 control register 2, then the transfer interval is inserted before the first data is transmitted/received and after the last data is transmitted/received. accordingly, regardless of the contents of the s busy2 output?s stb2 output function select bit, the transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the automatic transfer interval set bits of the serial i/o2 control register 3. (b) when using s stb2 output, regardless of the contents of the s busy2 output?s stb2 output function select bit, the transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the automatic transfer interval set bits of the serial i/o2 control register 3. (c) when using the combined output of s busy2 and s stb2 as the signal for each transfer data set, the transfer interval after completion of transmission/reception of the last data becomes 2 cycles longer than the value set by the automatic transfer interval set bits.
284 serial i/o2 (d) set the automatic transfer interval for each 1-byte data transfer as explained below to avoid incorrect transmit/receive of the serial data. ?not using fld controller keep the interval open for 5 cycles or more of the internal system clock from the rising edge of the last bit of 1-byte data. ?using fld controller a. gradation display off keep the interval open for 17 cycles or more of the internal system clock from the rising edge of the last bit of 1-byte data. b. gradation display on keep the interval open for 27 cycles or more of the internal system clock from the rising edge of the last bit of 1-byte data. tables 2.6.4 and 2.6.5 show the serial i/o2 control register 3 (address 0348 16 ) setting example. (e) when using an external clock, the automatic transfer interval setting becomes invalid. serial i/o2 control register 3, sio2con3 (address 0348 16 ) internal synchronous clock selection bits b7 b6 b5 0 0 0 : f(x in ) / 4 0 0 1 : f(x in ) / 8 0 1 0 : f(x in ) / 16 automatic transfer interval set bits (b4 to b0) 0 0 0 0 0 : 2 cycles of transfer clocks 0 0 0 0 1 : 3 cycles of transfer clocks 0 0 0 1 0 : 4 cycles of transfer clocks 0 0 0 1 1 : 5 cycles of transfer clocks 0 0 1 0 0 : 6 cycles of transfer clocks 0 0 1 0 1 : 7 cycles of transfer clocks 0 0 0 0 0 : 2 cycles of transfer clocks 0 0 0 0 1 : 3 cycles of transfer clocks 0 0 0 1 0 : 4 cycles of transfer clocks 0 0 0 0 0 : 2 cycles of transfer clocks not using fldc usable usable usable usable usable usable usable usable usable usable gradation display mode off prohibited prohibited prohibited usable usable usable prohibited usable usable usable gradation display mode on prohibited prohibited prohibited prohibited prohibited usable prohibited prohibited usable usable note: do not perform the following in the automatic transfer serial i/o mode: ?transfer within the ram area (addresses 00400 16 to 005ff 16 ) using the dmac ?transfer within the ram area (addresses 00400 16 to 005ff 16 ) using assembler instructions smovf and smovb. table 2.6.4 serial i/o2 control register 3, sio2con3 (address 0348 16 ) setting example (with internal synchronous clock) serial i/o2 control register 3, sio2con3 (address 0348 16 ); automatic transfer interval set bits not using fldc gradation display mode off gradation display mode on n cycles of transfer clocks transfer clock 5 n cycles 3 5 cycles of internal system clock transfer clock 5 n cycles 3 17 cycles of internal system clock transfer clock 5 n cycles 3 27 cycles of internal system clock table 2.6.5 serial i/o2 control register 3, sio2con3 (address 0348 16 ) setting example (with external synchronous clock)
285 serial i/o2 (a) write the value of the number of transfer-data decreased by 1 to the serial i/o2 transfer counter. (b) when using an external clock, after writing a value to the serial i/o2 register/transfer counter, wait for 5 or more cycles of the internal system clock before inputting the transfer clock to the serial i/o2 clock pin. the serial i/o automatic transfer interrupt request occurs when 0 is written to the serial i/o initializa- tion bit during an operation. use software to set this interrupt priority level to level 0 (interrupt dis- abled), or any other methods which will disable it. the occurrence timing of serial i/o automatic transfer interrupt request may be delayed: ?normally, the maximum delay is 17 cycles. in the fld gradation display mode on, the maximum delay increases to 27 cycles. ?if the occurrence timing of the serial i/o2 interrupt request is delayed, the flags and the signals which change simultaneously with the timing of the interrupt request, such as the serial transfer status flag and the handshake signals, will also change in accordance to the delay.
286 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.7 fld (vfd) controller 2.7.1 overview the fld controller drives and controls flds (fluorescent display). the following is the fld controller overview. (1) fldc port there are a total of 56 ports, consisting of 52 high-breakdown-voltage (hbv) ports and 4 cmos ports. 20 of the 52 hbv ports can be switched to normal ports, and all of the 4 cmos ports can be switched to general purpose ports. however, when using cmos ports as display pins, external drivers must be installed. ports p0, p1, p5 and p6, totaling 32 ports, have built-in pull-down resistors. (2) display pixel number (a) using all ports for fld output 28 segments ? 28 digits (segment number + digit number 56) (b) using digit pulse output function 40 segments ? 16 digits (segment number + digit number 56, however, digit number 16) (c) using p4 4 to p4 7 expansion function 52 segments ? 16 digits (segment number 52, digit number 16) (3) selection function the following selection functions can be applied to the fld controller. (a) tscan control two types of interrupt sources can be selected, using the tscan control bits (bits 2, 3 of address 0350 16 ): ?ld digit interrupt this is generated when the toff1 time for each timing ends (at rising edge of digit output). key scanning, which makes use of fld digits, can be applied by using each fld digit interrupt. ?ld blanking interrupt this is generated when the fld data pointer (address 0358 16 ) reaches ff 16 . the fld automatic display output is turned off for a duration of 1 ? tdisp, 2 ? tdisp, or 3 ? tdisp, depending on post-interrupt settings. key scanning, which makes use of fld segments, can be applied during this time. (b) timing number the following two types of timing can be selected: ?6-timing this timing is used when the display timing is 16 sets or less. ?2-timing this timing is used when the display timing is more than 16 sets. this can be used for up to 32 sets.
287 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (c) gradation display mode the gradation display mode can apply bright/dark display for each segment when the display timing is 16 or less. selection of gradation mode is as follows: gradation display mode on make sure to fix the timing number control bit (bit 4 of address 0350 16 ) to 0 as the maximum timing is 16. additionally, set the value to the toff2 time set register (address 0356 16 ) so that toff2 time can be less than tdisp time and more than toff1 time. gradation display mode off (d) hbv port drivability two types of drivability, strong or weak, can be selected for hbv ports. this setting is also valid when using hbv ports as general purpose ports. (e) p4 4 to p4 7 fld output reverse selecting this function enables the polarity reversal of the fld output from p4 4 to p4 7 . this function is useful for adjusting the polarity when using an externally installed driver. (f) p4 4 to p4 7 toff invalid selecting this function disables toff1 time and toff2 time and outputs display data for the duration of tdisp. (g) p9 7 dimmer signal output selecting this function outputs a signal from dimout (p9 7 ) to the decoder which, in turn, sends out the dimmer signal. the decoder controls this signal to enable the dimmer function. (h) toff section generate/not generate this function can be applied to all of the hbv ports (p0, p1, p2, p3, p4 0 to p4 3 , p5, p6) and cmos ports (p4 4 to p4 7 ). two types can be selected: generate toff section the toff section is generated. no toff section this function reduces unwanted noises generated whenever a port switches due to the combined capacity of the fld ports. when continuous data is output to each fld port, the toff1 section of the continuous parts is not generated. (i) toff2 set/reset change in gradation display mode, this function specifies either output (set) or 0 (reset) depending on toff2 time for fld output of dark display data (when gradation display control data is 1 ). two types can be selected: toff2set ram data is output to the fld output ports (set) at the time set by toff2 and is returned to 0 (reset) when the tdisp time ends. toff2reset ram data is output to the fld output ports (set) at the time set by toff1 and is returned to 0 (reset) at the time set by toff2.
288 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (4) expansion function the fld controller is equipped with an expansion function. (a) digit pulses output function digit pulses can be output automatically from ports p5 and p6. when the same number of 1s as the timing number are consecutively written from p6 0 to the digit output set registers (addresses 035c 16 , 035d 16 ), the contents of the fld automatic display ram for the ports that have been selected for digit output are disabled. the digit pulses are then automatically output. if a value exceeding the timing number for any port is set, the output of such port becomes l level. (b) p4 4 to p4 7 expansion function these ports have cmos output structure. this function provides 16 lines of fld digit outputs to these four ports by connecting the decoder which converts 4-bit data to 16-bit data. (5) registers related to fld controller figure 2.7.1 shows the memory map of fldc related-registers. figures 2.7.2 to 2.7.6 show fldc related-registers.
289 fld controller figure 2.7.1. memory map of fldc related-registers 0 3 5 4 1 6 0 3 5 5 1 6 0 3 5 6 1 6 0 3 5 7 1 6 0 3 5 8 1 6 0 3 5 c 1 6 t o f f 1 t i m e s e t r e g i s t e r ( t o f f 1 ) t o f f 2 t i m e s e t r e g i s t e r ( t o f f 2 ) f l d d a t a p o i n t e r ( f l d d p ) p o r t p 5 d i g i t o u t p u t s e t r e g i s t e r ( p 5 d o r ) 0 3 5 3 1 6 0 3 5 2 1 6 0 3 5 9 1 6 p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r ( p 2 f p r ) 0 3 5 a 1 6 p o r t p 3 f l d / p o r t s w i t c h r e g i s t e r ( p 3 f p r ) 0 3 5 b 1 6 p o r t p 4 f l d / p o r t s w i t c h r e g i s t e r ( p 4 f p r ) 0 0 5 0 1 6 0 3 5 0 1 6 f l d i n t e r r u p t c o n t r o l r e g i s t e r ( f l d i c ) f l d c m o d e r e g i s t e r ( f l d m ) t d i s p t i m e s e t r e g i s t e r ( t d i s p ) p o r t p 6 d i g i t o u t p u t s e t r e g i s t e r ( p 6 d o r ) 0 3 5 d 1 6 0 3 5 1 1 6 f l d o u t p u t c o n t r o l r e g i s t e r ( f l d c o n )
290 fld controller figure 2.7.2. fldc related-registers (1) f l d c m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t f l d m0 3 5 0 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 a u t o m a t i c d i s p l a y c o n t r o l b i t 0 : g e n e r a l - p u r p o s e m o d e 1 : a u t o m a t i c d i s p l a y m o d e f l d m 0 f l d m 1 f l d m 2 f l d m 3 d i s p l a y s t a r t b i t0 : s t o p d i s p l a y 1 : d i s p l a y ( s t a r t t o d i s p l a y b y s w i t c h i n g 0 t o 1 ) t s c a n c o n t r o l b i t s 0 0 : f l d d i g i t i n t e r r u p t ( a t r i s i n g e d g e o f e a c h d i g i t ) 0 1 : 1 x t d i s p 1 0 : 2 x t d i s p 1 1 : 3 x t d i s p 0 : 1 6 t i m i n g m o d e 1 : 3 2 t i m i n g m o d e t i m i n g n u m b e r c o n t r o l b i t g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 0 : n o t s e l e c t i n g 1 : s e l e c t i n g ( n o t e ) f l d m 4 f l d m 5 n o t e : w h e n a g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d , a n u m b e r o f t i m i n g i s m a x . 1 6 t i m i n g . ( s e t t h e t i m i n g n u m b e r c o n t r o l b i t t o 0 . ) t d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 3 2 1 : f ( x i n ) / 1 2 8 f l d m 6 h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 0 : d r i v a b i l i t y s t r o n g 1 : d r i v a b i l i t y w e a k f l d m 7 f l d o u t p u t c o n t r o l r e g i s t e r s y m b o la d d r e s sw h e n r e s e t f l d c o n0 3 5 1 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 f l d c o n 7 f l d c o n 5 f l d c o n 4 f l d c o n 2 f l d c o n0 f l d c o n 6 p 4 4 t o p 4 7 f l d o u t p u t r e v e r s e b i t p 4 4 t o p 4 7 f l d t o f f i s i n v a l i d b i t 0 : p e r f o r m n o r m a l l y 1 : t o f f i s i n v a l i d p 9 7 d i m m e r o u t p u t c o n t r o l b i t 0 : o u t p u t n o r m a l l y 1 : d i m m e r o u t p u t c m o s p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 0 : s e c t i o n o f t o f f d o e s n o t g e n e r a t e 1 : s e c t i o n o f t o f f g e n e r a t e s h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 0 : s e c t i o n o f t o f f d o e s n o t g e n e r a t e 1 : s e c t i o n o f t o f f g e n e r a t e s t o f f 2 s e t / r e s e t c h a n g e b i t 0 : g r a d a t i o n d i s p l a y d a t a i s r e s e t a t t o f f 2 ( s e t a t t o f f 1 ) 1 : g r a d a t i o n d i s p l a y d a t a i s s e t a t t o f f 2 ( r e s e t a t t o f f 1 ) w r 0 : o u t p u t n o r m a l l y 1 : r e v e r s e o u t p u t n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . f l d b l a n k i n g i n t e r r u p t ( a t f a l l i n g e d g e o f l a s t d i g i t ) } b 3 b 2 w r
291 fld controller figure 2.7.3. fldc related-registers (2) t o f f 1 t i m e s e t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t o f f 10 3 5 4 1 6 f f 1 6 w r b 7b 0 f u n c t i o n v a l u e s t h a t c a n b e s e t c o u n t s t o f f 1 t i m e . c o u n t s o u r c e i s s e l e c t e d b y t d i s p c o u n t e r c o u n t s o u r c e s e l e c t b i t . s u p p o s i n g t h a t t h e s e t v a l u e i s n 1 , t h e t o f f 1 t i m e i s e x p r e s s e d a s t o f f 1 = n 1 5 c o u n t s o u r c e . ( e x a m p l e ) t o f f 1 = 3 0 5 3 . 2 m s = 9 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z f l d c m o d e r e g i s t e r f l d m 6 = 0 ( f ( x i n ) / 3 2 s e l e c t e d a s t d i s p c o u n t e r c o u n t s o u r c e ) t o f f 1 t i m e s e t r e g i s t e r = 3 0 ( 1 e 1 6 ) 3 t o f f 1 6 t o f f 2 t i m e s e t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t o f f 20 3 5 6 1 6 f f 1 6 w r b 7b 0 c o u n t s t o f f 2 t i m e . c o u n t s o u r c e i s s e l e c t e d b y t d i s p c o u n t e r c o u n t s o u r c e s e l e c t b i t . s u p p o s i n g t h a t t h e s e t v a l u e i s n 2 , t h e t o f f 2 t i m e i s e x p r e s s e d a s t o f f 2 = n 2 5 c o u n t s o u r c e . t h i s s e t t i n g o f t o f f 2 t i m e a p p l i e s o n l y t o t h e f l d p o r t s a s t h e f o l l o w i n g : g r a d a t i o n d i s p l a y m o d e a n d t h e r a m v a l u e o f g r a d a t i o n d i s p l a y c o n t r o l i s 1 ( = d a r k d i s p l a y ) . ( e x a m p l e ) t o f f 2 = 1 8 0 5 3 . 2 m s = 5 7 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z f l d c m o d e r e g i s t e r f l d m 6 = 0 ( f ( x i n ) / 3 2 s e l e c t e d a s t d i s p c o u n t e r c o u n t s o u r c e ) t o f f 2 t i m e s e t r e g i s t e r = 1 8 0 ( b 4 1 6 ) 3 t o f f 1 6 f u n c t i o n v a l u e s t h a t c a n b e s e t t d i s p t i m e s e t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t d i s p0 3 5 2 1 6 0 0 1 6 w r b 7b 0 f u n c t i o n v a l u e s t h a t c a n b e s e t 0 1 6 t o f f 1 6 c o u n t s t d i s p t i m e . c o u n t s o u r c e i s s e l e c t e d b y t d i s p c o u n t e r c o u n t s o u r c e s e l e c t b i t . s u p p o s i n g t h a t t h e s e t v a l u e i s n , t h e t d i s p t i m e i s e x p r e s s e d a s t d i s p = ( n + 1 ) 5 c o u n t s o u r c e . w h e n r e a d i n g t h i s r e g i s t e r , t h e v a l u e i n t h e c o u n t e r o f t d i s p t i m e s e t r e g i s t e r i s r e a d o u t . ( e x a m p l e ) t d i s p = ( 2 0 0 + 1 ) 5 3 . 2 m s = 6 4 3 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z f l d c m o d e r e g i s t e r f l d m 6 = 0 ( f ( x i n ) / 3 2 s e l e c t e d a s t d i s p c o u n t e r c o u n t s o u r c e ) t d i s p t i m e s e t r e g i s t e r = 2 0 0 ( c 8 1 6 ) s y m b o la d d r e s sw h e n r e s e t t o f f 10 3 5 4 1 6 f f 1 6
292 fld controller f l d d a t a p o i n t e r s y m b o la d d r e s sw h e n r e s e t f l d d p0 3 5 8 1 6 i n d e t e r m i n a t e w r b 7b 0 c o u n t s f l d o u t p u t t i m i n g . s e t t h i s r e g i s t e r t o f l d o u t p u t d a t a - 1 . t h e s e t v a l u e i s w r i t t e n i n t o t h e f l d d a t a p o i n t e r r e l o a d r e g i s t e r . w h e n r e a d i n g t h i s r e g i s t e r , t h e v a l u e o f t h e f l d d a t a p o i n t e r i s r e a d o u t . 1 t o 1 f 1 6 n o t e : r e a d i n g t h e f l d d a t a p o i n t e r t a k e s o u t t h e c o u n t a t t h a t m o m e n t . f u n c t i o n v a l u e s t h a t c a n b e s e t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p 2 f p r0 3 5 9 1 6 0 0 1 6 w r b 7b 6b 5b 4b 3b 2b 1b 0 p 2 f p r 0 p 2 f p r 2 p 2 f p r 1 p 2 f p r 3 p 2 f p r 4 p 2 f p r 6 p 2 f p r 5 p 2 f p r 7 p o r t p 2 0 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 2 1 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 2 2 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 2 3 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 2 4 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 2 5 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 2 6 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 2 7 f l d / p o r t s w i t c h b i t b i t n a m ef u n c t i o n b i t s y m b o l 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 3 f l d / p o r t s w i t c h r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p 3 f p r0 3 5 a 1 6 0 0 1 6 w r b 7b 6b 5b 4b 3b 2b 1b 0 p 3 f p r 0 p 3 f p r 2 p 3 f p r 1 p 3 f p r 3 p 3 f p r 4 p 3 f p r 6 p 3 f p r 5 p 3 f p r 7 p o r t p 3 0 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 3 1 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 3 2 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 3 3 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 3 4 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 3 5 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 3 6 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 3 7 f l d / p o r t s w i t c h b i t b i t n a m ef u n c t i o n b i t s y m b o l figure 2.7.4. fldc related-registers (3)
293 fld controller 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 f l d / p o r t s w i t c h r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p 4 f p r0 3 5 b 1 6 0 0 1 6 w r b 7b 6b 5b 4b 3b 2b 1b 0 p 4 f p r 0 p 4 f p r 2 p 4 f p r 1 p 4 f p r 3 p 4 f p r 4 p 4 f p r 6 p 4 f p r 5 p 4 f p r 7 p o r t p 4 0 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 1 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 2 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 3 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 4 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 5 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 6 f l d / p o r t s w i t c h b i t 0 : n o r m a l p o r t 1 : f l d o u t p u t p o r t p o r t p 4 7 f l d / p o r t s w i t c h b i t b i t n a m ef u n c t i o n b i t s y m b o l 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 5 d i g i t o u t p u t s e t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p 5 d o r0 3 5 c 1 6 0 0 1 6 w r b 7b 6b 5b 4b 3b 2b 1b 0 p 5 d o r0 p 5 d o r 2 p 5 d o r 1 p 5 d o r 3 p 5 d o r 4 p 5 d o r 6 p 5 d o r 5 p 5 d o r 7 p o r t p 5 0 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 5 1 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 5 2 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 5 3 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 5 4 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 5 5 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 5 6 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 5 7 f l d / d i g i t s w i t c h b i t b i t n a m ef u n c t i o n b i t s y m b o l figure 2.7.5. fldc related-registers (4)
294 fld controller 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 6 d i g i t o u t p u t s e t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p 6 d o r0 3 5 d 1 6 0 0 1 6 w r b 7b 6b 5b 4b 3b 2b 1b 0 p 6d o r0 p 6d o r 2 p 6d o r 1 p 6d o r 3 p 6d o r 4 p 6d o r 6 p 6d o r 5 p 6d o r 7 p o r t p 6 0 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 6 1 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 6 2 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 6 3 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 6 4 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 6 5 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 6 6 f l d / d i g i t s w i t c h b i t 0 : f l d o u t p u t 1 : d i g i t o u t p u t p o r t p 6 7 f l d / d i g i t s w i t c h b i t b i t n a m ef u n c t i o n b i t s y m b o l figure 2.7.6. fldc related-registers (5)
295 fld controller this page kept blank for layout purposes.
296 fld controller 2.7.2 fld operation (fld automatic display and key-scan using segments) the fld controller can choose functions from those listed in table 2.7.1. the circled items are described in detail below. figure 2.7.7 shows the operation timing, and figures 2.7.8 to 2.7.10 show the set-up procedures. table 2.7.1. selectable functions note 1: when selecting the fld blanking interrupt, any one of 1 5 tdisp, 2 5 tdisp, or 3 5 tdisp can be selected as tscan time. note 2: when selecting the gradation display mode, make sure to use 16-timing as the timing number. i t e m s e t - u ps e t - u p o i t e m t s c a n c o n t r o l ( n o t e 1 ) f l d d i g i t i n t e r r u p t f l d b l a n k i n g i n t e r r u p t h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s t r o n g w e a k o t i m i n g n u m b e r1 6 - t i m i n g 3 2- t i m i n g o p 9 7 d i m m e r o u t p u tn o r m a l p o r t d i m m e r o u t p u t o t d i s p c o u n t e r c o u n t s o u r c e f ( x i n ) / 3 2 f ( x i n ) / 1 2 8 o h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e - r a t e / n o t g e n e r a t e se c t i o n o f t o f f d o e s n o t g e n e r a t e se c t i o n o f t o f f g e n e r a t e s o g r a d a t i o n d i s p l a y m o d e ( n o t e 2 ) n o t s e l e c t i n g se l e c t i n g o t o f f 2 s e t / r e s e t r e s e t a t t o f f 2 se t a t t o f f 2 o operation (1) the fld starts an automatic display when both the automatic display control bit and the display start bit are set to 1. (2) the display data, the contents from the first address through the last address, in the fld automatic display ram for each port is output to each port. the last address is the result of decreasing the number indicated in the fld data pointer from the first address. the grada- tion display control data is arranged at an address which is calculated by subtracting 70 16 from the stored address in the fld automatic display ram of the corresponding timing and pin. bright display is performed by setting 0, and dark display is performed by setting 1. however, the contents of the fld automatic display ram for ports p5 0 , p5 1 , and p6 0 to p6 7 are disabled by selection of the digit pulse output function, and the digit pulses are automati- cally output. (3) the fld data pointer counts down during tdisp time. when the count reaches ff 16 , the pointer is reloaded and starts counting over again. (4) the fld interrupt request bit is set to 1 simultaneously with the falling edge of the last timing. the fld automatic display output is turned off for a duration of 1 5 tdisp, 2 5 tdisp, or 3 5 tdisp, depending on post-interrupt settings. during this time, key scanning, which makes use of fld segments, can be applied. (5) during fld automatic display, the fld automatic display can be interrupted by writing 0 to the display start bit.
297 fld controller figure 2.7.7. operation timing of fld automatic display f l d 3 2 ( p 2 0 ) f l d 3 3 ( p 2 1 ) f l d 3 4 ( p 2 2 ) f l d 3 9 ( p 2 7 ) p 5 0 , p 5 1 p 6 0 ? 6 7 p 3 0 , p 3 1 p 2 0 p 2 7 p 3 4 p 3 7 s e g m e n t d i g i t r e c n l e v e l a m p m c h s u n m o n t u e w e d t h u f r i s a t l l r m 3 0 2 1 8 g r o u p k e y - m a t r i x p a n e l w i t h f l u o r e s c e n t d i s p l a y ( f l d ) l l l s e g m e n t c o n n e c t i o n e x a m p l e t d i s p t s c a n f l d b l a n k i n g i n t e r r u p t r e q u e s t o c c u r f l d 9 ( p 5 1 ) f l d 8 ( p 5 0 ) f l d 7 ( p 6 7 ) f l d 0 ( p 6 0 ) f l d 3 2 f l d 4 1 ( p 2 0 p 2 7 , p 3 0 , p 3 1 ) k e y - s c a n t o f f 1 t o f f 2 o p e r a t i o n e x a m p l e e n l a r g e d v i e w o f t s c a n s p e p
298 fld controller figure 2.7.8. set-up procedure for fld automatic display (1) 0 0 0 0 b 7b 0 p o r t p 3 d i r e c t i o n r e g i s t e r s e t - u p p o r t p 3 d i r e c t i o n r e g i s t e r [ a d d r e s s 0 3 e 7 1 6 ] p d 3 s e t p 3 4 p 3 7 t o i n p u t p o r t s f o r k e y - s c a n i n p u t 1 1 1 1 1 1 1 1 b 7b 0 d i s p l a y p i n/ p o r t s w i t c h o f p 2 , p 3 , p 5 a n d p 6 s e t - u p p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 9 1 6 ] p 2 f p r 0 0 0 0 0 0 1 1 b 7b 0 p o r t p 3 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 a 1 6 ] p 3 f p r s e t p 3 0 a n d p 3 1 t o f l d o u t p u t p o r t s ( f l d 4 0 , f l d 4 1 ) s e t p 3 2 p 3 7 t o n o r m a l i / o o u t p u t p o r t s 0 0 0 0 0 0 1 1 b 7b 0 p o r t p 5 d i g i t o u t p u t s e t r e g i s t e r [ a d d r e s s 0 3 5 c 1 6 ] p 5 d o r s e t p 5 0 a n d p 5 1 t o d i g i t o u t p u t p o r t s ( f l d 8 , f l d 9 ) s e t p 5 2 p 5 7 t o f l d o u t p u t p o r t s 1 1 1 1 1 1 1 1 s e t p 2 0 p 2 7 t o f l d o u t p u t p o r t s ( f l d 3 2 t o f l d 3 9 ) 1 1 1 1 1 1 1 1 b 7b 0 p o r t p 6 d i g i t o u t p u t s e t r e g i s t e r [ a d d r e s s 0 3 5 d 1 6 ] p 6 d o r s e t p 6 0 p 6 7 t o d i g i t o u t p u t p o r t s ( f l d 0 t o f l d 7 ) 1 0 1 0 1 1 0 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d c m o d e r e g i s t e r s e t - u p a u t o m a t i c d i s p l a y c o n t r o l b i t 1 : a u t o m a t i c d i s p l a y m o d e d i s p l a y s t a r t b i t 0 : s t o p d i s p l a y t s c a n c o n t r o l b i t s b 3 b 2 1 1 : 3 x t d i s p ; f l d b l a n k i n g i n t e r r u p t t i m i n g n u m b e r c o n t r o l b i t 0 : 1 6 t i m i n g m o d e g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 1 : s e l e c t i n g t d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 3 2 h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 1 : d r i v a b i l i t y w e a k 0 1 0 0 0 0 b 7b 0 f l d o u t p u t c o n t r o l r e g i s t e r [ a d d r e s s 0 3 5 1 1 6 ] f l d c o n f l d o u t p u t c o n t r o l r e g i s t e r s e t - u p p 4 4 t o p 4 7 f l d o u t p u t r e v e r s e b i t 0 : o u t p u t n o r m a l l y p 4 4 t o p 4 7 f l d t o f f i s i n v a l i d b i t 0 : p e r f o r m n o r m a l l y p 9 7 d i m m e r o u t p u t c o n t r o l b i t 0 : o u t p u t n o r m a l l y c m o s p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 0 : s e c t i o n o f t o f f d o e s n o t g e n e r a t e h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 1 : s e c t i o n o f t o f f g e n e r a t e s t o f f 2 s e t / r e s e t c h a n g e b i t 0 : g r a d a t i o n d i s p l a y d a t a i s r e s e t a t t o f f 2 ( s e t a t t o f f 1 ) c o n t i n u e d t o t h e n e x t p a g e
299 fld controller f l d d a t a p o i n t e r s e t - u p 1 1 1 1 1 1 1 1 b 7b 0 t d i s p , t o f f 1 a n d t o f f 2 t i m e s e t - u p 1 1 0 0 1 0 0 0 b 7b 0 t d i s p t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 2 1 6 ] t d i s p 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d d i s p l a y s t a r t d i s p l a y s t a r t b i t 1 : d i s p l a y 0 b 7b 0 f l d i n t e r r u p t c o n t r o l r e g i s t e r [ a d d r e s s 0 0 5 0 1 6 ] f l d i c f l d i n t e r r u p t c o n t r o l r e g i s t e r s e t - u p i n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t b 2 b 1 b 0 0 0 0 : l e v e l 0 ( i n t e r r u p t d i s a b l e d ) 0 0 1 : l e v e l 1 0 1 0 : l e v e l 2 0 1 1 : l e v e l 3 1 0 0 : l e v e l 4 1 0 1 : l e v e l 5 1 1 0 : l e v e l 6 1 1 1 : l e v e l 7 c o n t i n u e d f r o m t h e p r e v i o u s p a g e s e t c 8 1 6 ; t d i s p = ( 2 0 0 + 1 ) 5 c o u n t s o u r c e = 6 4 3 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 0 0 0 1 1 1 1 0 b 7b 0 t o f f 1 t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 4 1 6 ] t o f f 1 s e t 1 e 1 6 ; t o f f 1 = 3 0 5 c o u n t s o u r c e = 9 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 1 0 1 1 0 1 0 0 b 7b 0 t o f f 2 t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 6 1 6 ] t o f f 2 s e t b 4 1 6 ; t o f f 2 = 1 8 0 5 c o u n t s o u r c e = 5 7 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 0 0 0 0 1 0 0 1 b 7b 0 f l d d a t a p o i n t e r [ a d d r e s s 0 3 5 8 1 6 ] f l d d p s e t 9 = d i g i t n u m b e r 1 . i n t e r r u p t r e q u e s t b i t ( n o t e ) 0 : i n t e r r u p t n o t r e q u e s t e d n o t h i n g i s a s s i g n e d . n o t e : o n l y 0 c a n b e w r i t t e n t o t h i s b i t . ( d o n o t w r i t e 1 . ) f l d d i s p l a y s t a r t figure 2.7.9. set-up procedure for fld automatic display (2)
300 fld controller f l d b l a n k i n g i n t e r r u p t r o u t i n e p u s h re g i s t e r s a n d a n y o t h e r s e t - u p 0 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d c m o d e r e g i s t e r s e t - u p a u t o m a t i c d i s p l a y c o n t r o l b i t 0 : g e n e r a l - p u r p o s e m o d e 1 1 1 1 1 1 1 1 b 7b 0 p 2 , p 5 a n d p 6 s e t - u p 0 0 0 0 0 0 0 0 b 7b 0 0 0 0 0 0 0 0 0 b 7b 0 s e t p o r t s f o r k e y - s c a n t o n o r m a l p o r t s 0 0 b 7b 0 p o r t p 5 [ a d d r e s s 0 3 e 9 1 6 ] p 5 s e t l l e v e l t o p o r t s c o r r e s p o n d i n g t o d i g i t s p o r t p 6 [ a d d r e s s 0 3 e c 1 6 ] p 6 s e t l l e v e l t o p o r t s c o r r e s p o n d i n g t o d i g i t s p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 9 1 6 ] p 2 f p r 0 0 0 0 0 0 0 0 b 7b 0 p o r t p 2 [ a d d r e s s 0 3 e 4 1 6 ] p 2 o u t p u t l l e v e l f r o m p o r t s f o r k e y - s c a n k e y - s c a n p r o c e s s i n g 0 0 0 0 0 0 0 0 b 7b 0 p o r t p 2 [ a d d r e s s 0 3 e 4 1 6 ] p 2 o u t p u t l l e v e l f r o m p o r t s f o r k e y - s c a n p 2 s e t - u p 1 1 1 1 1 1 1 1 b 7b 0 s e t n o r m a l p o r t s t o f l d o u t p u t p o r t s p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 9 1 6 ] p 2 f p r 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d c m o d e r e g i s t e r s e t - u p a u t o m a t i c d i s p l a y c o n t r o l b i t 1 : a u t o m a t i c d i s p l a y m o d e r t i figure 2.7.10. set-up procedure for key-scan processing
301 fld controller this page kept blank for layout purposes.
302 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.7.3 fld operation (fld automatic display and key-scan using digits) the fld controller can choose functions from those listed in table 2.7.2. the circled items are described in detail below. figure 2.7.11 shows the operation timing, and figures 2.7.12 and 2.7.13 show the set-up procedures. table 2.7.2. selectable functions note 1: when selecting the fld blanking interrupt, any one of 1 5 tdisp, 2 5 tdisp, or 3 5 tdisp can be selected as tscan time. note 2: when selecting the gradation display mode, make sure to use 16-timing as the timing number. operation (1) the fld starts an automatic display when both the automatic display control bit and the display start bit are set to 1. (2) the display data, the contents from the first address through the last address, in the fld automatic display ram for each port is output to each port. the last address is the result of decreasing the number indicated in the fld data pointer from the first address. the grada- tion display control data is arranged at an address which is calculated by subtracting 70 16 from the stored address in the fld automatic display ram of the corresponding timing and pin. bright display is performed by setting 0, and dark display is performed by setting 1. however, the contents of the fld automatic display ram for ports p5 0 , p5 1 , and p6 0 to p6 7 are disabled by selection of the digit pulse output function, and the digit pulses are automati- cally output. (3) the fld data pointer counts down during tdisp time. when the count reaches ff 16 , the pointer is reloaded and starts counting over again. (4) the fld interrupt request bit is set to 1 simultaneously with the end of toff1 time (at the rising edge of a digit) for each timing. key scanning, which makes use of fld digits, can be applied by using each fld digit interrupt. (5) during fld automatic display, the fld automatic display can be interrupted by writing 0 to the display start bit. i t e m s e t - u ps e t - u p o i t e m t s c a n c o n t r o l ( n o t e 1 ) f l d d i g i t i n t e r r u p t f l d b l a n k i n g i n t e r r u p t h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s t r o n g w e a k o t i m i n g n u m b e r1 6 - t i m i n g 3 2- t i m i n g o p 9 7 d i m m e r o u t p u tn o r m a l p o r t d i m m e r o u t p u t o t d i s p c o u n t e r c o u n t s o u r c e f ( x i n ) / 3 2 f ( x i n ) / 1 2 8 o h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e - r a t e / n o t g e n e r a t e se c t i o n o f t o f f d o e s n o t g e n e r a t e se c t i o n o f t o f f g e n e r a t e s o g r a d a t i o n d i s p l a y m o d e ( n o t e 2 ) n o t s e l e c t i n g se l e c t i n g o t o f f 2 s e t / r e s e t r e s e t a t t o f f 2 se t a t t o f f 2 o
303 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.7.11. operation timing of fld automatic display p 2 0 ? 2 7 p 3 0 , p 3 1 p 5 0 , p 5 1 p 6 0 p 6 7 p 3 4 p 3 7 s e g m e n t d i g i t d i g i t s p e p r e c n l e v e l a m p m c h s u n m o n t u e w e d t h u f r i s a t l l r m 3 0 2 1 8 gr o u p k e y - m a t r i x p a n e l w i t h f l u o r e s c e n t d i s p l a y ( f l d ) l l l t d i s p t s c a n = 0 m s f l d 9 ( p 5 1 ) f l d 8 ( p 5 0 ) f l d 7 ( p 6 7 ) f l d 0 ( p 6 0 ) f l d 3 2 f l d 4 1 ( p 2 0 p 2 7 , p 3 0 , p 3 1 ) t o f f 2 t o f f 1 f l d d i g i t i n t e r r u p t r e q u e s t o c c u r f l d d i g i t i n t e r r u p t r e q u e s t o c c u r f l d d i g i t i n t e r r u p t r e q u e s t o c c u r f l d d i g i t i n t e r r u p t r e q u e s t o c c u r c o n n e c t i o n e x a m p l e o p e r a t i o n e x a m p l e
304 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.7.12. set-up procedure for fld automatic display (1) 0 0 0 0 b 7b 0 p o r t p 3 d i r e c t i o n r e g i s t e r s e t - u p p o r t p 3 d i r e c t i o n r e g i s t e r [ a d d r e s s 0 3 e 7 1 6 ] p d 3 s e t p 3 4 p 3 7 t o i n p u t p o r t s f o r k e y - s c a n i n p u t 1 1 1 1 1 1 1 1 b 7b 0 d i s p l a y p i n/ p o r t s w i t c h o f p 2 , p 3 , p 5 a n d p 6 s e t - u p p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 9 1 6 ] p 2 f p r 0 0 0 0 0 0 1 1 b 7b 0 p o r t p 3 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 a 1 6 ] p 3 f p r s e t p 3 0 a n d p 3 1 t o f l d o u t p u t p o r t s ( f l d 4 0 , f l d 4 1 ) s e t p 3 2 p 3 7 t o n o r m a l i / o o u t p u t p o r t s 0 0 0 0 0 0 1 1 b 7b 0 p o r t p 5 d i g i t o u t p u t s e t r e g i s t e r [ a d d r e s s 0 3 5 c 1 6 ] p 5 d o r s e t p 5 0 a n d p 5 1 t o d i g i t o u t p u t p o r t s ( f l d 8 , f l d 9 ) s e t p 5 2 p 5 7 t o f l d o u t p u t p o r t s 1 1 1 1 1 1 1 1 s e t p 2 0 p 2 7 t o f l d o u t p u t p o r t s ( f l d 3 2 t o f l d 3 9 ) 1 1 1 1 1 1 1 1 b 7b 0 p o r t p 6 d i g i t o u t p u t s e t r e g i s t e r [ a d d r e s s 0 3 5 d 1 6 ] p 6 d o r s e t p 6 0 p 6 7 t o d i g i t o u t p u t p o r t s ( f l d 0 t o f l d 7 ) 1 0 1 0 0 0 0 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d c m o d e r e g i s t e r s e t - u p a u t o m a t i c d i s p l a y c o n t r o l b i t 1 : a u t o m a t i c d i s p l a y m o d e d i s p l a y s t a r t b i t 0 : s t o p d i s p l a y t s c a n c o n t r o l b i t s b 3 b 2 0 0 : f l d d i g i t i n t e r r u p t t i m i n g n u m b e r c o n t r o l b i t 0 : 1 6 t i m i n g m o d e g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 1 : s e l e c t i n g t d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 3 2 h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 1 : d r i v a b i l i t y w e a k 0 1 0 0 0 0 b 7b 0 f l d o u t p u t c o n t r o l r e g i s t e r [ a d d r e s s 0 3 5 1 1 6 ] f l d c o n f l d o u t p u t c o n t r o l r e g i s t e r s e t - u p p 4 4 t o p 4 7 f l d o u t p u t r e v e r s e b i t 0 : o u t p u t n o r m a l l y p 4 4 t o p 4 7 f l d t o f f i s i n v a l i d b i t 0 : p e r f o r m n o r m a l l y p 9 7 d i m m e r o u t p u t c o n t r o l b i t 0 : o u t p u t n o r m a l l y c m o s p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 0 : s e c t i o n o f t o f f d o e s n o t g e n e r a t e h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 1 : s e c t i o n o f t o f f g e n e r a t e s t o f f 2 s e t / r e s e t c h a n g e b i t 0 : g r a d a t i o n d i s p l a y d a t a i s r e s e t a t t o f f 2 ( s e t a t t o f f 1 ) c o n t i n u e d t o t h e n e x t p a g e
305 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.7.13. set-up procedure for fld automatic display (2) f l d d a t a p o i n t e r s e t - u p 1 1 1 1 1 1 1 1 b 7b 0 t d i s p , t o f f 1 a n d t o f f 2 t i m e s e t - u p 1 1 0 0 1 0 0 0 t d i s p t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 2 1 6 ] t d i s p 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d d i s p l a y s t a r t d i s p l a y s t a r t b i t 1 : d i s p l a y 0 b 7b 0 f l d i n t e r r u p t c o n t r o l r e g i s t e r [ a d d r e s s 0 0 5 0 1 6 ] f l d i c f l d i n t e r r u p t c o n t r o l r e g i s t e r s e t - u p i n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t b 2 b 1 b 0 0 0 0 : l e v e l 0 ( i n t e r r u p t d i s a b l e d ) 0 0 1 : l e v e l 1 0 1 0 : l e v e l 2 0 1 1 : l e v e l 3 1 0 0 : l e v e l 4 1 0 1 : l e v e l 5 1 1 0 : l e v e l 6 1 1 1 : l e v e l 7 c o n t i n u e d f r o m t h e p r e v i o u s p a g e s e t c 8 1 6 ; t d i s p = ( 2 0 0 + 1 ) 5 c o u n t s o u r c e = 6 4 3 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 0 0 0 1 1 1 1 0 t o f f 1 t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 4 1 6 ] t o f f 1 s e t 1 e 1 6 ; t o f f 1 = 3 0 5 c o u n t s o u r c e = 9 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 1 0 1 1 0 1 0 0 t o f f 2 t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 6 1 6 ] t o f f 2 s e t b 4 1 6 ; t o f f 2 = 1 8 0 5 c o u n t s o u r c e = 5 7 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 0 0 0 0 1 0 0 1 b 7b 0 f l d d a t a p o i n t e r [ a d d r e s s 0 3 5 8 1 6 ] f l d d p s e t 9 = d i g i t n u m b e r 1 . i n t e r r u p t r e q u e s t b i t ( n o t e ) 0 : i n t e r r u p t n o t r e q u e s t e d n o t h i n g i s a s s i g n e d . n o t e : o n l y 0 c a n b e w r i t t e n t o t h i s b i t . ( d o n o t w r i t e 1 . ) f l d d i s p l a y s t a r t
306 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.7.4 fld operation (fld display and key-scan using segment by software) fld display and key-scan using the timer a0 interrupt are explained in detail below. figure 2.7.14 shows the operation timing, and figures 2.7.15 to 2.7.17 show the set-up procedures. operation (1) set both the automatic display control bit and the display start bit to 0. (2) output segment data and digit data from each port during the timer a0 interrupt processing. (3) after finishing display of all digits, perform key-scan within during the timer a0 interrupt processing.
307 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.7.14. operation timing of fld display p 5 0 , p 5 1 p 6 0 ? 6 7 p 3 0 , p 3 1 p 2 0 p 2 7 p 3 4 p 3 7 s e g m e n t d i g i t s p e p r e c n l e v e l a m p m c h s u n m o n t u e w e d t h u f r i s a t l l r m 3 0 2 1 8 gr o u p k e y - m a t r i x p a n e l w i t h f l u o r e s c e n t d i s p l a y ( f l d ) l l l s e g m e n t p 5 1 p 5 0 p 6 7 p 6 0 p 2 0 p 2 7 , p 3 0 , p 3 1 k e y - s c a n p 2 0 p 2 1 p 2 2 p 2 7 c o n n e c t i o n e x a m p l e o p e r a t i o n e x a m p l e e n l a r g e d v i e w o f k e y - s c a n
308 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 0 0 0 0 b 7b 0 p o r t p 3 d i r e c t i o n r e g i s t e r s e t - u p p o r t p 3 d i r e c t i o n r e g i s t e r [ a d d r e s s 0 3 e 7 1 6 ] p d 3 s e t p 3 0 a n d p 3 1 t o o u t p u t p o r t s f o r s e g m e n t o u t p u t b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d c m o d e r e g i s t e r s e t - u p a u t o m a t i c d i s p l a y c o n t r o l b i t 0 : g e n e r a l - p u r p o s e m o d e d i s p l a y s t a r t b i t 0 : s t o p d i s p l a y h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 1 : d r i v a b i l i t y w e a k b 7b 0 c l o c k p r e s c a l e r r e s e t f l a g [ a d d r e s s 0 3 8 1 1 6 ] c p s r f c o n t i n u e d t o t h e n e x t p a g e 11 s e t p 3 4 p 3 7 t o i n p u t p o r t s f o r k e y - s c a n i n p u t t i m e r a 0 m o d e r e g i s t e r [ a d d r e s s 0 3 9 6 1 6 ] t a 0 m r ti m e r m o d e ( t i m e r a 0 ) a n d f u n c t i o n s s e t - u p s e l e c t i o n o f t i m e r m o d e p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a 0 o u t p i n i s a n o r m a l p o r t p i n ) g a t e f u n c t i o n s e l e c t b i t b 4 b 3 0 0 : 0 1 : g a t e f u n c t i o n n o t a v a i l a b l e ( t a 0 i n p i n i s a n o r m a l p o r t p i n ) 0 ( m u s t a l w a y s b e 0 i n t i m e r m o d e ) c o u n t s o u r c e s e l e c t b i t b 7 b 6 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 c o u n t s o u r c e p e r i o d f ( x i n ) : 1 0 m h z f ( x c i n ) : 3 2 . 7 6 8 k h z b 7b 6 c o u n t s o u r c e 1 0 0 n s 8 0 0 n s 3 . 2 m s 9 7 6 . 5 6 m s 00 01 10 11 f 1 f 8 f 3 2 f c 3 2 0 b 7b 0 0 0 0 0 b 7b 0 ( b 1 5 )( b 8 ) b 7b 0 t i m e r a 0 r e g i s t e r [ a d d r e s s 0 3 8 7 1 6 , 0 3 8 6 1 6 ] t a 0 c a n b e s e t t o 0 0 0 0 1 6 t o f f f f 1 6 di v i d e r a t i o s e t - u p cl o c k p r e s c a l e r r e s e t f l a g s e t - u p ( t h i s f u n c t i o n i s e f f e c t i v e w h e n f c 3 2 i s s e l e c t e d a s t h e c o u n t s o u r c e . r e s e t t h e p r e s c a l e r f o r g e n e r a t i n g f c 3 2 b y d i v i d i n g t h e x c i n b y 3 2 . ) c l o c k p r e s c a l e r r e s e t f l a g 0 : n o e f f e c t 1 : p r e s c a l e r i s r e s e t ( w h e n r e a d , t h e v a l u e i s 0 ) 1 00 figure 2.7.15. set-up procedure for fld display (1)
309 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 1 b 7b 0 c o u n t s t a r t f l a g [ a d d r e s s 0 3 8 0 1 6 ] t a b s r c o u n t s t a r t f l a g s e t - u p 0 b 7b 0 t a 0 i n t e r r u p t c o n t r o l r e g i s t e r [ a d d r e s s 0 0 5 5 1 6 ] t a 0 i c t a 0 i n t e r r u p t c o n t r o l r e g i s t e r s e t - u p i n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t b 2 b 1 b 0 0 0 0 : l e v e l 0 ( i n t e r r u p t d i s a b l e d ) 0 0 1 : l e v e l 1 0 1 0 : l e v e l 2 0 1 1 : l e v e l 3 1 0 0 : l e v e l 4 1 0 1 : l e v e l 5 1 1 0 : l e v e l 6 1 1 1 : l e v e l 7 c o n t i n u e d f r o m t h e p r e v i o u s p a g e i n t e r r u p t r e q u e s t b i t ( n o t e ) 0 : i n t e r r u p t n o t r e q u e s t e d n o t h i n g i s a s s i g n e d . n o t e : o n l y 0 c a n b e w r i t t e n t o t h i s b i t . ( d o n o t w r i t e 1 . ) t i m e r a 0 c o u n t s t a r t f l a g 1 : s t a r t s c o u n t i n g 1 figure 2.7.16. set-up procedure for fld display (2)
310 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r t a 0 i n t e r r u p t r o u t i n e p u s h re g i s t e r s a n d a n y o t h e r s e t - u p 1 1 1 1 1 1 1 1 b 7b 0 p 2 , p 3 , p 5 a n d p 6 s e t - u p 0 0 b 7b 0 0 0 b 7b 0 p o r t p 2 [ a d d r e s s 0 3 e 4 1 6 ] p 2 s e t 0 t o p o r t s c o r r e s p o n d i n g t o s e g m e n t s p o r t p 3 [ a d d r e s s 0 3 e 5 1 6 ] p 3 0 0 0 0 0 0 0 0 b 7b 0 p o r t p 2 [ a d d r e s s 0 3 e 4 1 6 ] p 2 s e t s e g m e n t d a t a s e g m e n t d a t a s e t - u p 0 0 b 7b 0 p o r t p 3 [ a d d r e s s 0 3 e 5 1 6 ] p 3 r t i 000000 s e t 0 t o p o r t s c o r r e s p o n d i n g t o s e g m e n t s 0 0 b 7b 0 p o r t p 5 [ a d d r e s s 0 3 e 9 1 6 ] p 5 s e t 0 t o p o r t s c o r r e s p o n d i n g t o d i g i t s 1 1 1 1 1 1 1 1 b 7b 0 0 0 b 7b 0 p o r t p 6 [ a d d r e s s 0 3 e c 1 6 ] p 6 s e t 0 t o p o r t s c o r r e s p o n d i n g t o d i g i t s 000000 s e t s e g m e n t d a t a 0 0 b 7b 0 p o r t p 5 [ a d d r e s s 0 3 e 9 1 6 ] p 2 s e t d i g i t d a t a d i g i t d a t a s e t - u p 0 0 b 7b 0 p o r t p 6 [ a d d r e s s 0 3 e c 1 6 ] p 6 s e t d i g i t d a t a 000000 figure 2.7.17. set-up procedure for key-scan processing
311 fld controller m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r this page kept blank for layout purposes.
312 fld controller 2.7.5 fld operation (display with digit expander m35501fp) the fld controller can choose functions from those listed in table 2.7.3. the circled items are described in detail below. figure 2.7.18 shows the connection example and figure 2.7.19 shows the operation timing, and figures 2.7.20 and 2.7.21 show the set-up procedures. remarks: also refer to the m35501fp data sheet on http://www.infomicom.mesc.co.jp table 2.7.3. selectable functions note 1: when selecting the fld blanking interrupt, any one of 1 5 tdisp, 2 5 tdisp, or 3 5 tdisp can be selected as tscan time. note 2: when selecting the gradation display mode, make sure to use 16-timing as the timing number. operation (1) the fld starts an automatic display when both the automatic display control bit and the display start bit are set to 1. (2) the display data, the contents from the first address through the last address, in the fld automatic display ram for each port is output to each port. the last address is the result of decreasing the number indicated in the fld data pointer from the first address. the grada- tion display control data is arranged at an address which is calculated by subtracting 70 16 from the stored address in the fld automatic display ram of the corresponding timing and pin. bright display is performed by setting 0, and dark display is performed by setting 1. (3) the fld data pointer counts down during tdisp time. when the count reaches ff 16 , the pointer is reloaded and starts counting over again. (4) supply signals to the reset pin and sel pin of the m35501fp from ports p7 0 and p7 1 , respectively. supply the dimmer signal to the clk pin from the dim out (p9 7 ). (5) during fld automatic display, the fld automatic display can be interrupted by writing 0 to the display start bit. i t e m s e t - u ps e t - u p o i t e m t s c a n c o n t r o l ( n o t e 1 ) f l d d i g i t i n t e r r u p t f l d b l a n k i n g i n t e r r u p t h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s t r o n g w e a k o t i m i n g n u m b e r1 6 - t i m i n g 3 2- t i m i n g o p 9 7 d i m m e r o u t p u tn o r m a l p o r t d i m m e r o u t p u t o t d i s p c o u n t e r c o u n t s o u r c e f ( x i n ) / 3 2 f ( x i n ) / 1 2 8 o h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e - r a t e / n o t g e n e r a t e se c t i o n o f t o f f d o e s n o t g e n e r a t e se c t i o n o f t o f f g e n e r a t e s o g r a d a t i o n d i s p l a y m o d e ( n o t e 2 ) n o t s e l e c t i n g se l e c t i n g o t o f f 2 s e t / r e s e t r e s e t a t t o f f 2 se t a t t o f f 2 o
313 fld controller figure 2.7.18. connection example of fld automatic display (1) d i g i t ( 1 6 ) f l u o r e s c e n t d i s p l a y ( f l d ) p 3 0 p 3 7 p 1 0 p 1 7 p 0 0 p 0 7 p 2 0 p 2 7 s e g m e n t ( 5 2 ) m 3 0 2 1 8 g r o u p m 3 5 5 0 1 f p c l k s e l r e s e t d i g 0 d i g 1 5 p 4 0 p 4 3 d i m o u t p 7 0 p 7 1 o v f i n p 6 0 p 6 7 p 5 0 p 5 7 o v f o u t c o n n e c t i o n e x a m p l e
314 fld controller r e s e t s e l o v f i n o v f o u t f l d 0 f l d 5 1 ( p 0 0 p 0 7 , p 1 0 p 1 7 , p 2 0 p 2 7 , p 3 0 p 3 7 , p 4 0 p 4 3 , p 5 0 p 5 7 , p 6 0 p 6 7 ) c l k d i g 0 d i g 3 d i g 1 2 d i g 1 d i g 2 d i g 1 3 d i g 1 4 d i g 1 5 m 3 0 2 1 8 g r o u p m 3 5 5 0 1 f p o p e r a t i o n e x a m p l e e n l a r g e d v i e w t d i s p t o f f 2 t o f f 1 c l k d i g 0 d i g 1 d i g 2 d i g 1 5 m 3 5 5 0 1 f p m 3 0 2 1 8 g r o u p f l d 0 f l d 5 1 ( p 0 0 p 0 7 , p 1 0 p 1 7 , p 2 0 p 2 7 , p 3 0 p 3 7 , p 4 0 p 4 3 , p 5 0 p 5 7 , p 6 0 p 6 7 ) figure 2.7.19. operation timing of fld automatic display
315 fld controller figure 2.7.20. set-up procedure for fld automatic display (1) 1 1 1 1 1 1 1 1 b 7b 0 d i s p l a y p i n / p o r t s w i t c h o f p 2 , p 3 , p 4 , p 5 a n d p 6 s e t - u p p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 9 1 6 ] p 2 f p r 1 1 1 1 1 1 1 1 b 7b 0 p o r t p 3 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 a 1 6 ] p 3 f p r s e t p 3 0 p 3 7 t o f l d o u t p u t p o r t s ( f l d 4 0 t o f l d 4 7 ) 0 0 0 0 0 0 0 0 b 7b 0 p o r t p 5 d i g i t o u t p u t s e t r e g i s t e r [ a d d r e s s 0 3 5 c 1 6 ] p 5 d o r s e t p 5 0 p 5 7 t o f l d o u t p u t p o r t s ( f l d 8 t o f l d 1 5 ) 1 1 1 1 1 1 1 1 s e t p 2 0 p 2 7 t o f l d o u t p u t p o r t s ( f l d 3 2 t o f l d 3 9 ) 0 0 0 0 0 0 0 0 b 7b 0 p o r t p 6 d i g i t o u t p u t s e t r e g i s t e r [ a d d r e s s 0 3 5 d 1 6 ] p 6 d o r s e t p 6 0 p 6 7 t o f l d o u t p u t p o r t s ( f l d 0 t o f l d 7 ) 1 0 1 0 0 0 0 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d c m o d e r e g i s t e r s e t - u p a u t o m a t i c d i s p l a y c o n t r o l b i t 1 : a u t o m a t i c d i s p l a y m o d e d i s p l a y s t a r t b i t 0 : s t o p d i s p l a y t s c a n c o n t r o l b i t s b 3 b 2 0 0 : f l d d i g i t i n t e r r u p t t i m i n g n u m b e r c o n t r o l b i t 0 : 1 6 t i m i n g m o d e g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 1 : s e l e c t i n g t d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 3 2 h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 1 : d r i v a b i l i t y w e a k c o n t i n u e d t o t h e n e x t p a g e 0 0 0 0 1 1 1 1 b 7b 0 p o r t p 4 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 b 1 6 ] p 4 f p r s e t p 4 4 p 4 7 t o n o r m a l i / o p o r t s s e t p 4 0 p 4 3 t o f l d o u t p u t p o r t s ( f l d 4 8 t o f l d 5 1 ) 1 1 b 7b 0 p o r t p 7 d i r e c t i o n r e g i s t e r [ a d d r e s s 0 3 e f 1 6 ] p d 7 s e t p 7 1 t o o u t p u t p o r t ( f o r s e l s i g n a l o f m 3 5 5 0 1 ) s e t p 7 0 t o o u t p u t p o r t ( f o r r e s e t s i g n a l o f m 3 5 5 0 1 ) m 3 5 5 0 1 i n i t i a l i z a t i o n 0 0 b 7b 0 p o r t p 7 [ a d d r e s s 0 3 e d 1 6 ] p 7 o u t p u t s e l s i g n a l l o f m 3 5 5 0 1 o u t p u t r e s e t s i g n a l o f m 3 5 5 0 1 ( n o t e ) n o t e : t o r e m o v e r e s e t s t a t e , a f t e r r e t a i n i n g l l e v e l f o r 2 m s o r m o r e , o u t p u t h l e v e l w h e n c l k s i g n a l = l .
316 fld controller figure 2.7.21. set-up procedure for fld automatic display (2) f l d d a t a p o i n t e r s e t - u p 1 1 1 1 1 1 1 1 b 7b 0 t d i s p , t o f f 1 a n d t o f f 2 t i m e s e t - u p 1 1 0 0 1 0 0 0 b 7b 0 t d i s p t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 2 1 6 ] t d i s p 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d d i s p l a y s t a r t d i s p l a y s t a r t b i t 1 : d i s p l a y c o n t i n u e d f r o m t h e p r e v i o u s p a g e s e t c 8 1 6 ; t d i s p = ( 2 0 0 + 1 ) 5 c o u n t s o u r c e = 6 4 3 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 0 0 0 1 1 1 1 0 b 7b 0 t o f f 1 t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 4 1 6 ] t o f f 1 s e t 1 e 1 6 ; t o f f 1 = 3 0 5 c o u n t s o u r c e = 9 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 1 0 1 1 0 1 0 0 b 7b 0 t o f f 2 t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 6 1 6 ] t o f f 2 s e t b 4 1 6 ; t o f f 2 = 1 8 0 5 c o u n t s o u r c e = 5 7 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 0 0 0 0 1 1 1 1 b 7b 0 f l d d a t a p o i n t e r [ a d d r e s s 0 3 5 8 1 6 ] f l d d p s e t 1 5 = d i g i t n u m b e r 1 . f l d d i s p l a y s t a r t 0 1 0 1 0 0 b 7b 0 f l d o u t p u t c o n t r o l r e g i s t e r [ a d d r e s s 0 3 5 1 1 6 ] f l d c o n f l d o u t p u t c o n t r o l r e g i s t e r s e t - u p p 4 4 t o p 4 7 f l d o u t p u t r e v e r s e b i t 0 : o u t p u t n o r m a l l y p 4 4 t o p 4 7 f l d t o f f i s i n v a l i d b i t 0 : p e r f o r m n o r m a l l y p 9 7 d i m m e r o u t p u t c o n t r o l b i t 1 : d i m m e r o u t p u t c m o s p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 0 : s e c t i o n o f t o f f d o e s n o t g e n e r a t e h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 1 : s e c t i o n o f t o f f g e n e r a t e s t o f f 2 s e t / r e s e t c h a n g e b i t 0 : g r a d a t i o n d i s p l a y d a t a i s r e s e t a t t o f f 2 ( s e t a t t o f f 1 )
317 fld controller this page kept blank for layout purposes.
318 fld controller 2.7.6 fld operation (display with digit expander m35501fp: column discrepancy) the fld controller can choose functions from those listed in table 2.7.4. the circled items are described in detail below. figure 2.7.22 shows the connection example and figure 2.7.23 shows the operation timing, and figures 2.7.24 and 2.7.27 show the set-up procedures. remarks: also refer to the m35501fp data sheet on http://www.infomicom.mesc.co.jp table 2.7.4. selectable functions note 1: when selecting the fld blanking interrupt, any one of 1 5 tdisp, 2 5 tdisp, or 3 5 tdisp can be selected as tscan time. note 2: when selecting the gradation display mode, make sure to use 16-timing as the timing number. operation (1) the fld starts an automatic display when both the automatic display control bit and the display start bit are set to 1. (2) the display data, the contents from the first address through the last address, in the fld automatic display ram for each port is output to each port. the last address is the result of decreasing the number indicated in the fld data pointer from the first address. the grada- tion display control data is arranged at an address which is calculated by subtracting 70 16 from the stored address in the fld automatic display ram of the corresponding timing and pin. bright display is performed by setting 0, and dark display is performed by setting 1. (3) the fld data pointer counts down during tdisp time. when the count reaches ff 16 , the pointer is reloaded and starts counting over again. (4) supply signals to the reset pin and sel pin of the m35501fp from ports p7 0 and p7 1 , respectively. supply the dimmer signal to the clk pin from the dim out (p9 7 ). (5) input the ovf out output of the m35501fp to tb2 in (p7 2 ) and count the input signals as a count source with timer b2. generate the timer a0 interrupt at fld display intervals and confirm the value of timer b2. if the value is incorrect, reset the m35501fp. (6) during fld automatic display, the fld automatic display can be interrupted by writing 0 to the display start bit. i t e m s e t - u ps e t - u p o i t e m t s c a n c o n t r o l ( n o t e 1 ) f l d d i g i t i n t e r r u p t f l d b l a n k i n g i n t e r r u p t h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s t r o n g w e a k o t i m i n g n u m b e r1 6 - t i m i n g 3 2- t i m i n g o p 9 7 d i m m e r o u t p u tn o r m a l p o r t d i m m e r o u t p u t o t d i s p c o u n t e r c o u n t s o u r c e f ( x i n ) / 3 2 f ( x i n ) / 1 2 8 o h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e - r a t e / n o t g e n e r a t e se c t i o n o f t o f f d o e s n o t g e n e r a t e se c t i o n o f t o f f g e n e r a t e s o g r a d a t i o n d i s p l a y m o d e ( n o t e 2 ) n o t s e l e c t i n g se l e c t i n g o t o f f 2 s e t / r e s e t r e s e t a t t o f f 2 se t a t t o f f 2 o
319 fld controller figure 2.7.22. connection example of fld automatic display d i g i t ( 1 6 ) f l u o r e s c e n t d i s p l a y ( f l d ) p 3 0 p 3 7 p 1 0 p 1 7 p 0 0 p 0 7 p 2 0 p 2 7 s e g m e n t ( 5 2 ) m 3 0 2 1 8 g r o u p m 3 5 5 0 1 f p c l k s e l r e s e t d i g 0 d i g 1 5 p 4 0 p 4 3 d i m o u t p 7 0 p 7 1 o v f i n p 6 0 p 6 7 p 5 0 p 5 7 o v f o u t c o n n e c t i o n e x a m p l e t b 2 i n
320 fld controller r e s e t s e l o v f i n o v f o u t c l k d i g 0 d i g 1 d i g 1 4 d i g 1 5 m 3 5 5 0 1 f p r e s e t s e l o v f i n o v f o u t c l k d i g 0 d i g 1 d i g 1 4 d i g 1 5 m 3 5 5 0 1 f p c o l u m n d i s c r e p a n c y o c c u r n o i s e f l d 0 f l d 5 1 ( p 0 0 p 0 7 , p 1 0 p 1 7 , p 2 0 p 2 7 , p 3 0 p 3 7 , p 4 0 p 4 3 , p 5 0 p 5 7 , p 6 0 p 6 7 ) m 3 0 2 1 8 g r o u p c o r r e c t op e r a t i o n e x a m p l e i n co r r e c t op e r a t i o n e x a m p l e f l d 0 f l d 5 1 ( p 0 0 p 0 7 , p 1 0 p 1 7 , p 2 0 p 2 7 , p 3 0 p 3 7 , p 4 0 p 4 3 , p 5 0 p 5 7 , p 6 0 p 6 7 ) m 3 0 2 1 8 g r o u p figure 2.7.23. operation timing of fld automatic display
321 fld controller figure 2.7.24. set-up procedure for fld automatic display (1) 1 1 1 1 1 1 1 1 b 7b 0 d i s p l a y p i n / p o r t s w i t c h o f p 2 , p 3 , p 4 , p 5 a n d p 6 s e t - u p p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 9 1 6 ] p 2 f p r 1 1 1 1 1 1 1 1 b 7b 0 p o r t p 3 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 a 1 6 ] p 3 f p r s e t p 3 0 p 3 7 t o f l d o u t p u t p o r t s ( f l d 4 0 t o f l d 4 7 ) 0 0 0 0 0 0 0 0 b 7b 0 p o r t p 5 d i g i t o u t p u t s e t r e g i s t e r [ a d d r e s s 0 3 5 c 1 6 ] p 5 d o r s e t p 5 0 p 5 7 t o f l d o u t p u t p o r t s ( f l d 8 t o f l d 1 5 ) 1 1 1 1 1 1 1 1 s e t p 2 0 p 2 7 t o f l d o u t p u t p o r t s ( f l d 3 2 t o f l d 3 9 ) 0 0 0 0 0 0 0 0 b 7b 0 p o r t p 6 d i g i t o u t p u t s e t r e g i s t e r [ a d d r e s s 0 3 5 d 1 6 ] p 6 d o r s e t p 6 0 p 6 7 t o f l d o u t p u t p o r t s ( f l d 0 t o f l d 7 ) 1 0 1 0 0 0 0 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d c m o d e r e g i s t e r s e t - u p a u t o m a t i c d i s p l a y c o n t r o l b i t 1 : a u t o m a t i c d i s p l a y m o d e d i s p l a y s t a r t b i t 0 : s t o p d i s p l a y t s c a n c o n t r o l b i t s b 3 b 2 0 0 : f l d d i g i t i n t e r r u p t t i m i n g n u m b e r c o n t r o l b i t 0 : 1 6 t i m i n g m o d e g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 1 : s e l e c t i n g t d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 3 2 h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 1 : d r i v a b i l i t y w e a k c o n t i n u e d t o t h e n e x t p a g e 0 0 0 0 1 1 1 1 b 7b 0 p o r t p 4 f l d / p o r t s w i t c h r e g i s t e r [ a d d r e s s 0 3 5 b 1 6 ] p 4 f p r s e t p 4 4 p 4 7 t o n o r m a l i / o p o r t s s e t p 4 0 p 4 3 t o f l d o u t p u t p o r t s ( f l d 4 8 t o f l d 5 1 ) 1 1 b 7b 0 p o r t p 7 d i r e c t i o n r e g i s t e r [ a d d r e s s 0 3 e f 1 6 ] p d 7 s e t p 7 1 t o o u t p u t p o r t ( f o r s e l s i g n a l o f m 3 5 5 0 1 ) s e t p 7 0 t o o u t p u t p o r t ( f o r r e s e t s i g n a l o f m 3 5 5 0 1 ) m 3 5 5 0 1 i n i t i a l i z a t i o n 0 0 b 7b 0 p o r t p 7 [ a d d r e s s 0 3 e d 1 6 ] p 7 o u t p u t s e l s i g n a l l o f m 3 5 5 0 1 o u t p u t r e s e t s i g n a l o f m 3 5 5 0 1 ( n o t e ) n o t e : t o r e m o v e r e s e t s t a t e , a f t e r r e t a i n i n g l l e v e l f o r 2 m s o r m o r e , o u t p u t h l e v e l w h e n c l k s i g n a l = l .
322 fld controller figure 2.7.25. set-up procedure for fld automatic display (2) f l d d a t a p o i n t e r s e t - u p 1 1 1 1 1 1 1 1 b 7b 0 t d i s p , t o f f 1 a n d t o f f 2 t i m e s e t - u p 1 1 0 0 1 0 0 0 b 7b 0 t d i s p t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 2 1 6 ] t d i s p c o n t i n u e d f r o m t h e p r e v i o u s p a g e s e t c 8 1 6 ; t d i s p = ( 2 0 0 + 1 ) 5 c o u n t s o u r c e = 6 4 3 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 0 0 0 1 1 1 1 0 b 7b 0 t o f f 1 t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 4 1 6 ] t o f f 1 s e t 1 e 1 6 ; t o f f 1 = 3 0 5 c o u n t s o u r c e = 9 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 1 0 1 1 0 1 0 0 b 7b 0 t o f f 2 t i m e s e t r e g i s t e r [ a d d r e s s 0 3 5 6 1 6 ] t o f f 2 s e t b 4 1 6 ; t o f f 2 = 1 8 0 5 c o u n t s o u r c e = 5 7 6 m s c o n d i t i o n s : f ( x i n ) = 1 0 m h z c o u n t s o u r c e = f ( x i n ) / 3 2 = 3 . 2 m s 1 1 1 1 1 1 1 1 b 7b 0 0 0 0 0 1 1 1 1 b 7b 0 f l d d a t a p o i n t e r [ a d d r e s s 0 3 5 8 1 6 ] f l d d p s e t 1 5 = d i g i t n u m b e r 1 . c o n t i n u e d t o t h e n e x t p a g e 0 1 0 1 0 0 b 7b 0 f l d o u t p u t c o n t r o l r e g i s t e r [ a d d r e s s 0 3 5 1 1 6 ] f l d c o n f l d o u t p u t c o n t r o l r e g i s t e r s e t - u p p 4 4 t o p 4 7 f l d o u t p u t r e v e r s e b i t 0 : o u t p u t n o r m a l l y p 4 4 t o p 4 7 f l d t o f f i s i n v a l i d b i t 0 : p e r f o r m n o r m a l l y p 9 7 d i m m e r o u t p u t c o n t r o l b i t 1 : d i m m e r o u t p u t c m o s p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 0 : s e c t i o n o f t o f f d o e s n o t g e n e r a t e h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 1 : s e c t i o n o f t o f f g e n e r a t e s t o f f 2 s e t / r e s e t c h a n g e b i t 0 : g r a d a t i o n d i s p l a y d a t a i s r e s e t a t t o f f 2 ( s e t a t t o f f 1 ) 0 0 1 1 b 7b 0 t i m e r b 2 m o d e r e g i s t e r [ a d d r e s s 0 3 9 d 1 6 ] t b 2 m r ev e n t c o u n t e r m o d e ( t i m e r b 2 ) a n d f u n c t i o n s s e t - u p 0 0 0 0 s e l e c t i o n o f e v e n t c o u n t e r m o d e c o u n t p o l a r i t y s e l e c t b i t b 3 b 2 0 1 : c o u n t s e x t e r n a l s i g n a l s r i s i n g e d g e s i n v a l i d i n e v e n t c o u n t e r m o d e e v e n t c l o c k s e l e c t 0 : i n p u t f r o m t b 2 i n p i n ( n o t e ) n o t e : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 .
323 fld controller t i m e r a 0 m o d e r e g i s t e r [ a d d r e s s 0 3 9 6 1 6 ] t a 0 m r ti m e r m o d e ( t i m e r a 0 ) a n d f u n c t i o n s s e t - u p s e l e c t i o n o f t i m e r m o d e p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a 0 o u t p i n i s a n o r m a l p o r t p i n ) g a t e f u n c t i o n s e l e c t b i t b 4 b 3 0 0 : 0 1 : g a t e f u n c t i o n n o t a v a i l a b l e ( t a 0 i n p i n i s a n o r m a l p o r t p i n ) 0 ( m u s t a l w a y s b e 0 i n t i m e r m o d e ) c o u n t s o u r c e s e l e c t b i t b 7 b 6 0 1 : f 8 0 b 7b 0 0 0 0 0 b 7b 0 ( b 1 5 )( b 8 ) b 7b 0 t i m e r a 0 r e g i s t e r [ a d d r e s s 0 3 8 7 1 6 , 0 3 8 6 1 6 ] t a 0 se t 3 2 4 0 1 6 di v i d e r a t i o ( t i m e r a 0 ) s e t - u p c o n t i n u e d f r o m t h e p r e v i o u s p a g e b 7b 0 ( b 1 5 )( b 8 ) b 7b 0 t i m e r b 2 r e g i s t e r [ a d d r e s s 0 3 9 5 1 6 , 0 3 9 4 1 6 ] t b 2 s e t f f f f 1 6 di v i d e r a t i o ( t i m e r b 2 ) s e t - u p 1 0 1 b 7b 0 c o u n t s t a r t f l a g [ a d d r e s s 0 3 8 0 1 6 ] t a b s r c o u n t s t a r t f l a g s e t - u p 0 b 7b 0 t a 0 i n t e r r u p t c o n t r o l r e g i s t e r [ a d d r e s s 0 0 5 5 1 6 ] t a 0 i c t i m e r a 0 i n t e r r u p t c o n t r o l r e g i s t e r s e t - u p i n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t b 2 b 1 b 0 0 0 0 : l e v e l 0 ( i n t e r r u p t d i s a b l e d ) 0 0 1 : l e v e l 1 0 1 0 : l e v e l 2 0 1 1 : l e v e l 3 1 0 0 : l e v e l 4 1 0 1 : l e v e l 5 1 1 0 : l e v e l 6 1 1 1 : l e v e l 7 i n t e r r u p t r e q u e s t b i t ( n o t e ) 0 : i n t e r r u p t n o t r e q u e s t e d n o t h i n g i s a s s i g n e d . n o t e : o n l y 0 c a n b e w r i t t e n t o t h i s b i t . ( d o n o t w r i t e 1 . ) t i m e r a 0 c o u n t s t a r t f l a g 1 : s t a r t s c o u n t i n g 1 1 t i m e r b 2 c o u n t s t a r t f l a g 1 : s t a r t s c o u n t i n g 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d d i s p l a y s t a r t d i s p l a y s t a r t b i t 1 : d i s p l a y f l d d i s p l a y s t a r t figure 2.7.26. set-up procedure for fld automatic display (3)
324 fld controller t a 0 i n t e r r u p t r o u t i n e p u s h re g i s t e r s a n d a n y o t h e r s e t - u p r t i t i m e r b 2 d a t a c h e c k ? 0 0 b 7b 0 m 3 5 5 0 1 i n i t i a l i z a t i o n 0 1 b 7b 0 p o r t p 7 [ a d d r e s s 0 3 e d 1 6 ] p 7 o u t p u t s e l s i g n a l l o f m 3 5 5 0 1 o u t p u t r e s e t s i g n a l h o f m 3 5 5 0 1 ( n o t e ) n o t e : t o r e m o v e r e s e t s t a t e , a f t e r r e t a i n i n g l l e v e l f o r 2 m s o r m o r e , o u t p u t h l e v e l w h e n c l k s i g n a l = l . p o r t p 7 [ a d d r e s s 0 3 e d 1 6 ] p 7 o u t p u t s e l s i g n a l l o f m 3 5 5 0 1 o u t p u t r e s e t s i g n a l l o f m 3 5 5 0 1 s e t d i s p l a y d a t a t o f l d a u t o m a t i c d i s p l a y r a m b 7b 0 ( b 1 5 )( b 8 ) b 7b 0 t i m e r b 2 r e g i s t e r [ a d d r e s s 0 3 9 5 1 6 , 0 3 9 4 1 6 ] t b 2 s e t f f f f 1 6 di v i d e r a t i o ( t i m e r b 2 ) s e t - u p 1 b 7b 0 c o u n t s t a r t f l a g [ a d d r e s s 0 3 8 0 1 6 ] t a b s r c o u n t s t a r t f l a g s e t - u p t i m e r a 0 c o u n t s t a r t f l a g 1 : s t a r t s c o u n t i n g 1 1 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d d i s p l a y s t a r t d i s p l a y s t a r t b i t 1 : d i s p l a y 0 b 7b 0 f l d c m o d e r e g i s t e r [ a d d r e s s 0 3 5 0 1 6 ] f l d m f l d d i s p l a y s t o p d i s p l a y s t a r t b i t 0 : s t o p d i s p l a y p o p re g i s t e r s c o r r e c t d a t a ( f e 1 6 ) i n co r r e c t d a t a ( e x c e p t f e 1 6 ) figure 2.7.27. set-up procedure for fld automatic display when detecting column discrepancy
325 fld controller 2.7.7 precautions for fld controller (1) set a value of 03 16 or more to the toff1 time set register. (2) when displaying in the gradation display mode, select the 16-timing mode with the timing number control bit.
326 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.8 a-d converter table 2.8.1. conversion time every operation clock note 1: the number of conversion cycles per one analog input pin. note 2: the conversion time per one analog input pin (when f ad = f(x in ) = 10 mhz) 2.8.1 overview the a-d converter used in the M30218 group operates on a successive conversion basis. the following is an overview of the a-d converter. (1) mode the a-d converter operates in one of five modes: (a) one-shot mode carries out a-d conversion on input level of one specified pin only once. (b) repetition mode repeatedly carries out a-d conversion on input level of one specified pin. (c) one-shot sweep mode carries out a-d conversion on input level of two or more specified pins only once. (d) repeated sweep mode 0 repeatedly carries out a-d conversion on input level of two or more pins. (e) repeated sweep mode 1 repeatedly carries out a-d conversion on input level of two or more pins. this mode is different from the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of conversion times. (2) operation clock the operation clock can be selected from the following: f ad , divide-by-2 f ad , and divide-by-4 f ad . the f ad frequency is equal to that of the cpus main clock. (3) conversion time number of conversion for a-d convertor varies depending on resolution as given. table 2.8.1 shows relation between the a-d converter operation clock and conversion time. sample & hold function selected: 33 cycles for 10-bit resolution, or 28 cycles for 8-bit resolution no sample & hold function: 59 cycles for 10-bit resolution, or 49 cycles for 8-bit resolution frequency selection bit 0 a-d converter's operation clock min. conversion cycles (note 1) min. conversion time (note 2) 8-bit mode 8-bit mode 10-bit mode 10-bit mode 0 1 f ad = 4 f ad f ad = 2 f ad 28 x f ad 33 x f ad 11.2s 13.2s 6.6s 5.6s frequency selection bit 1 0 1 invalid f ad = f ad 2.8s 3.3s
327 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (4) functions selection (a) sample & hold function sample & hold function samples input voltage when a-d conversion starts and carries out a-d conversion on the voltage sampled. when a-d conversion starts, input voltage is sampled for 3 cycles of the operation clock. when the sample & hold function is selected, set the operation clock for a-d conversion to 1 mhz or higher. (b) 8-bit a-d to 10-bit a-d switching function either 8-bit resolution or 10-bit resolution can be selected. when 8-bit resolution is selected, the 8 higher-order bits of the 10-bit a-d are subjected to a-d conversion. the equations for 10-bit resolu- tion and 8-bit resolution are given below: 10-bit resolution (vref x n / 2 10 ) C (vref x 0.5 / 10 10 ) (n = 1 to 1023), 0 (n = 0) 8-bit resolution (vref x n / 2 8 ) C (vref x 0.5 / 2 10 ) (n = 1 to 255), 0 (n = 0) (c) connecting or cutting vref cutting vref allows decrease of the current flowing into the a-d converter. to decrease the microcomputer's power consumption, cut vref. to carry out a-d conversion, start a-d conversion 1 m s or longer after connecting vref. the following are exsamples in which functions (a) through (c) are selected: ? one-shot mode ................................................................................................................ ......... p332 ? repeat mode, software trigger ................................................................................................ . p334 ? one-shot sweep mode, software trigger ................................................................................... p336 ? repeated sweep mode 0, software trigger ............................................................................... p338 ? repeated sweep mode 1, software trigger ............................................................................... p340
328 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.1. memory map of a-d converter-related registers (5) input to a-d converter and direction register to use the a-d converter, set the direction register of the relevant port to input. (6) pins related to a-d converter (a) an 0 pin through an 7 pin input pins of the a-d converter (b) avcc pin power source pin of the analog section (c) v ref pin input pin of reference voltage (d) avss pin gnd pin of the analog section (7) a-d converter and related registers figure 2.8.1 shows the memory map of a-d converter-related registers, and figures 2.8.2 through 2.8.4 show a-d converter-related registers. 004e 16 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d4 16 03d5 16 03d6 16 03d7 16 a-d register 7 (ad7) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) a-d control register 0 (adcon0) a-d control register 1 (adcon1) a-d control register 2 (adcon2) a-d conversion interrupt control register (adic)
329 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.2. a-d converter-related registers (1) a - d c o n t r o l r e g i s t e r 0 ( n o t e ) s y m b o la d d r e s sw h e n r e s e t a d c o n 00 3 d 6 1 6 0 0 0 0 0 x x x 2 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 a n a l o g i n p u t p i n s e l e c t b i t 0 0 0 : a n 0 i s s e l e c t e d 0 0 1 : a n 1 i s s e l e c t e d 0 1 0 : a n 2 i s s e l e c t e d 0 1 1 : a n 3 i s s e l e c t e d 1 0 0 : a n 4 i s s e l e c t e d 1 0 1 : a n 5 i s s e l e c t e d 1 1 0 : a n 6 i s s e l e c t e d 1 1 1 : a n 7 i s s e l e c t e d c h 0 c h 1 c h 2 a - d o p e r a t i o n m o d e s e l e c t b i t 0 0 0 : o n e - s h o t m o d e 0 1 : r e p e a t m o d e 1 0 : s i n g l e s w e e p m o d e 1 1 : r e p e a t s w e e p m o d e 0 r e p e a t s w e e p m o d e 1 m d 0 m d 1 m u s t a l w a y s b e 0 . a d s t a - d c o n v e r s i o n s t a r t f l a g0 : a - d c o n v e r s i o n d i s a b l e d 1 : a - d c o n v e r s i o n s t a r t e d f r e q u e n c y s e l e c t b i t 00 : f a d / 4 i s s e l e c t e d 1 : f a d / 2 i s s e l e c t e d c k s 0 w r b 2 b 1 b 0 b 4 b 3 n o t e : i f t h e a - d c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g a - d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . 0
330 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.3. a-d converter-related registers (2) a - d c o n t r o l r e g i s t e r 1 ( n o t e ) s y m b o l a d d r e s sw h e n r e s e t a d c o n 10 3 d 7 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 a - d s w e e p p i n s e l e c t b i t s c a n 0 s c a n 1 m d 2 b i t s 8 / 1 0 - b i t m o d e s e l e c t b i t0 : 8 - b i t m o d e 1 : 1 0 - b i t m o d e v c u t v r e f c o n n e c t b i t a - d o p e r a t i o n m o d e s e l e c t b i t 1 0 : a n y m o d e o t h e r t h a n r e p e a t s w e e p m o d e 1 1 : r e p e a t s w e e p m o d e 1 0 : v r e f n o t c o n n e c t e d 1 : v r e f c o n n e c t e d m u s t a l w a y s b e 0 . w r w h e n s i n g l e s w e e p a n d r e p e a t s w e e p m o d e 0 a r e s e l e c t e d 0 0 : a n 0 , a n 1 ( 2 p i n s ) 0 1 : a n 0 t o a n 3 ( 4 p i n s ) 1 0 : a n 0 t o a n 5 ( 6 p i n s ) 1 1 : a n 0 t o a n 7 ( 8 p i n s ) b 1 b 0 w h e n r e p e a t s w e e p m o d e 1 i s s e l e c t e d 0 0 : a n 0 ( 1 p i n ) 0 1 : a n 0 , a n 1 ( 2 p i n s ) 1 0 : a n 0 t o a n 2 ( 3 p i n s ) 1 1 : a n 0 t o a n 3 ( 4 p i n s ) b 1 b 0 f r e q u e n c y s e l e c t b i t 10 : f a d / 2 o r f a d / 4 i s s e l e c t e d 1 : f a d i s s e l e c t e d c k s 1 n o t e : i f t h e a - d c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g a - d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . 0 0
331 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.4. a-d converter-related registers (3) e i g h t l o w - o r d e r b i t s o f a - d c o n v e r s i o n r e s u l t a - d c o n t r o l r e g i s t e r 2 ( n o t e ) s y m b o la d d r e s sw h e n r e s e t a d c o n 20 3 d 4 1 6 x x x x x x x 0 2 b i t n a m ef u n c t i o n b i t s y m b o lw r b 7b 6b 5b 4b 3b 2b 1b 0 a - d c o n v e r s i o n m e t h o d s e l e c t b i t 0 w i t h o u t s a m p l e a n d h o l d 1 w i t h s a m p l e a n d h o l d s m p n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . a - d r e g i s t e r i s y m b o la d d r e s sw h e n r e s e t a d i ( i = 0 t o 7 ) 0 3 c 0 1 6 t o 0 3 c f 1 6 i n d e t e r m i n a t e f u n c t i o nw r ( b 1 5 ) b 7 b 7b 0b 0 ( b 8 ) d u r i n g 1 0 - b i t m o d e t w o h i g h - o r d e r b i t s o f a - d c o n v e r s i o n r e s u l t n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . d u r i n g 8 - b i t m o d e w h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e n o t e : i f t h e a - d c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g a - d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e .
332 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in one-shot mode, choose functions from those listed in table 2.8.2. operations of the circled items are described below. figure 2.8.5 shows the operation timing, and figure 2.8.6 shows the set-up procedure. 2.8.2 operation of a-d converter (one-shot mode) figure 2.8.5. operation timing of one-shot mode operation table 2.8.2. choosed functions (1) setting the a-d conversion start flag to 1 causes the a-d converter to begin operating. (2) after a-d conversion is completed, the content of the successive comparison register (con- version result) is transmitted to a-d register i. at this time, the a-d conversion interrupt re- quest bit goes to 1. also, the a-d conversion start flag goes to 0, and the a-d converter stops operating. item set-up operation clock f ad divided-by-4 f ad / divided- by-2 f ad / f ad 8-bit / 10-bit sample & hold not activated activated o o resolution analog input pin one of an 0 pin to an 7 pin o o a-d conversion start flag ? ? a-d conversion interrupt request bit a-d register i ? ? cleared to ??when interrupt request is accepted, or cleared by software result f ad 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles set to ??by software (1) start a-d conversion (2) a-d conversion is complete note: when f ad frequency is less than 1mh z , sample and hold function cannot be selected. conversion rate per analog input pin is 49 f ad cycles for 8-bit resolution and 59 f ad cycles for 10-bit resolution.
333 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.6. set-up procedure of one-shot mode b7 b0 1 setting a-d conversion start flag a-d control register 0 [address 03d6 16 ] adcon0 a-d conversion start flag 1 : a-d conversion started reading conversion result eight low-order bits of a-d conversion result b7 b0 (b15) (b8) b7 b0 a-d register 0 [address 03c1 16 , 03c0 16 ] ad0 a-d register 1 [address 03c3 16 , 03c2 16 ] ad1 a-d register 2 [address 03c5 16 , 03c4 16 ] ad2 a-d register 3 [address 03c7 16 , 03c6 16 ] ad3 a-d register 4 [address 03c9 16 , 03c8 16 ] ad4 a-d register 5 [address 03cb 16 , 03ca 16 ] ad5 a-d register 6 [address 03cd 16 , 03cc 16 ] ad6 a-d register 7 [address 03cf 16 , 03ce 16 ] ad7 during 10-bit mode two high-order bits of a-d conversion result during 8-bit mode when read, the content is indeterminate start a-d conversion stop a-d conversion b7 b0 setting a-d control register 0 and a-d control register 1 a-d control register 0 [address 03d6 16 ] adcon0 analog input pin select bit (note) 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected b2 b1 b0 b7 b0 a-d control register 1 [address 03d7 16 ] adcon1 a-d operation mode select bit 1 (note) 0 (must always be ??in one-shot mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected one-shot mode is selected (note) nothing is arranged for this bit. fix ??to this bit. a-d conversion start flag 0 : a-d conversion disabled frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected 0 000 invalid in one-shot mode vref connect bit 1 : vref connected nothing is arranged for these bits. fix ??to these bits. 00 0 1 b7 b0 selecting sample and hold a-d control register 2 [address 03d4 16 ] adcon2 a-d conversion method select bit 1 : with sample and hold 1 note: rewrite to analog input pin select bit after changing a-d operation mode.
334 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in repeat mode, choose functions from those listed in table 2.8.3. operations of the circled items are described below. figure 2.8.7 shows timing chart, and figure 2.8.8 shows the set-up procedure. 2.8.3 operation of a-d converter (in repeat mode) (1) setting the a-d conversion start flag to 1 causes the a-d converter to start operating. (2) after the first conversion is completed, the content of the successive comparison register (conversion result) is transmitted to a-d register i. the a-d conversion interrupt request bit does not go to 1. (3) the a-d converter continues operating until the a-d conversion start flag is set to 0 by software. the conversion result is transmitted to a-d register i every time a conversion is completed. table 2.8.3. choosed functions operation figure 2.8.7. operation timing of repeat mode a-d conversion start flag ? ? a-d register i result set to ??by software f ad 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles (1) start a-d conversion (2) conversion result is transferred to the a-d register (3) a-d conversion is complete cleared to ??by software a-d conversion result stop convert convert convert stop note: when f ad frequency is less than 1mhz, sample and hold function cannot be selected. conversion rate per analog input pin is 49 f ad cycles for 8-bit resolution and 59 f ad cycles for 10-bit resolution. 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles item set-up operation clock f ad divided-by-4 f ad / divided- by-2 f ad / f ad 8-bit / 10-bit sample & hold not activated activated o o resolution analog input pin one of an 0 pin to an 7 pin o o
335 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.8. set-up procedure of repeat mode b7 b0 1 setting a-d conversion start flag a-d control register 0 [address 03d6 16 ] adcon0 a-d conversion start flag 1 : a-d conversion started transmitting conversion result to a-d register i eight low-order bits of a-d conversion result b7 b0 (b15) (b8) b7 b0 a-d register 0 [address 03c1 16 , 03c0 16 ] ad0 a-d register 1 [address 03c3 16 , 03c2 16 ] ad1 a-d register 2 [address 03c5 16 , 03c4 16 ] ad2 a-d register 3 [address 03c7 16 , 03c6 16 ] ad3 a-d register 4 [address 03c9 16 , 03c8 16 ] ad4 a-d register 5 [address 03cb 16 , 03ca 16 ] ad5 a-d register 6 [address 03cd 16 , 03cc 16 ] ad6 a-d register 7 [address 03cf 16 , 03ce 16 ] ad7 during 10-bit mode two high-order bits of a-d conversion result during 8-bit mode when read, the content is indeterminate b7 b0 setting a-d control register 0 and a-d control register 1 a-d control register 0 [address 03d6 16 ] adcon0 analog input pin select bit (note) 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected b2 b1 b0 b7 b0 a-d control register 1 [address 03d7 16 ] adcon1 a-d operation mode select bit 1 (note) 0 (must always be ??in repeat mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected repeat mode is selected (note) a-d conversion start flag 0 : a-d conversion disabled frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected 0 001 invalid in repeat mode vref connect bit 1 : vref connected nothing is arranged for these bits. fix ??to these bits 00 0 1 nothing is arranged for this bit. fix ??to this bit. start a-d conversion b7 b0 0 setting a-d conversion start flag a-d control register 0 [address 03d6 16 ] adcon0 a-d conversion start flag 0 : a-d conversion disabled stop a-d conversion b7 b0 selecting sample and hold a-d control register 2 [address 03d4 16 ] adcon2 a-d conversion method select bit 1 : with sample and hold 1 note: rewrite to analog input pin select bit after changing a-d operation mode.
336 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in single sweep mode, choose functions from those listed in table 2.8.4. operations of the circled items are described below. figure 2.8.9 shows timing chart, and figure 2.8.10 shows the set-up procedure. 2.8.4 operation of a-d converter (in single sweep mode) figure 2.8.9. operation timing of single sweep mode operation (1) setting the a-d conversion start flag to 1 causes the a-d converter to start the conversion on voltage input to the an 0 pin. (2) after the a-d conversion of voltage input to the an 0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to a-d register 0. the a-d converter converts all analog input pins selected by the user. the conversion result is trans- mitted to a-d register i corresponding to each pin, every time conversion on one pin is com- pleted. (3) when the a-d conversion on all the analog input pins selected is completed, the a-d conver- sion interrupt request bit goes to 1. at this time, the a-d conversion start flag goes to 0. the a-d converter stops operating. table 2.8.4. choosed functions item item set-up set-up operation clock f ad divided-by-4 f ad / divided- by-2 f ad / f ad 8-bit / 10-bit o resolution analog input pin an 0 and an 1 (2 pins) / an 0 to an 3 (4 pins) / an 0 to an 5 (6 pins) / an 0 to an 7 (8 pins) o o sample & hold not activated activated o cleared to ??when interrupt request is accepted, or cleared by software a-d conversion start flag ? ? a-d register 0 a-d register 1 f ad a-d register i result result result set to ??by software 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles (1) start a-d conversion after a-d conversion on an 0 pin is complete, a-d converter begins converting all pins selected a-d conversion is complete (2) note: when f ad frequency is less than 1mh z , sample and hold function cannot be selected. conversion rate per analog input pin is 49 f ad cycles for 8-bit resolution and 59 f ad cycles for 10-bit resolution. (3) a-d conversion interrupt request bit ? ?
337 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.10. set-up procedure of single sweep mode b7 b0 1 setting a-d conversion start flag a-d control register 0 [address 03d6 16 ] adcon0 a-d conversion start flag 1 : a-d conversion started reading conversion result eight low-order bits of a-d conversion result b7 b0 (b15) (b8) b7 b0 a-d register 0 [address 03c1 16 , 03c0 16 ] ad0 a-d register 1 [address 03c3 16 , 03c2 16 ] ad1 a-d register 2 [address 03c5 16 , 03c4 16 ] ad2 a-d register 3 [address 03c7 16 , 03c6 16 ] ad3 a-d register 4 [address 03c9 16 , 03c8 16 ] ad4 a-d register 5 [address 03cb 16 , 03ca 16 ] ad5 a-d register 6 [address 03cd 16 , 03cc 16 ] ad6 a-d register 7 [address 03cf 16 , 03ce 16 ] ad7 during 10-bit mode two high-order bits of a-d conversion result during 8-bit mode when read, the content is indeterminate start a-d conversion stop a-d conversion b7 b0 setting a-d control register 0 and a-d control register 1 a-d control register 0 [address 03d6 16 ] adcon0 a-d sweep pin select bit (note) 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 b7 b0 a-d control register 1 [address 03d7 16 ] adcon1 a-d operation mode select bit 1 (note) 0 (must always be ??in single sweep mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected single sweep mode is selected (note) nothing is arranged for this bit. fix ??to this bit. a-d conversion start flag 0 : a-d conversion disabled frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected 0 010 vref connect bit 1 : vref connected 00 0 1 invalid in single sweep mode b7 b0 selecting sample and hold a-d control register 2 [address 03d4 16 ] adcon2 a-d conversion method select bit 1 : with sample and hold 1 note: rewrite to analog input pin select bit after changing a-d operation mode. nothing is arranged for these bits. fix ??to these bits.
338 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in repeat sweep mode 0, choose functions from those listed in table 2.8.5. operations of the circled items are described below. figure 2.8.11 shows timing chart, and figure 2.8.12 shows the set-up procedure. 2.8.5 operation of a-d converter (in repeat sweep mode 0) operation table 2.8.5. choosed functions (1) setting the a-d conversion start flag to 1 causes the a-d converter to start the conversion on voltage input to the an 0 pin. (2) after the a-d conversion of voltage input to the an 0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to a-d register 0. (3) the a-d converter converts all pins selected by the user. the conversion result is transmitted to a-d register i corresponding to each pin every time a-d conversion on the pin is com- pleted. the a-d conversion interrupt request bit does not go to 1. (4) the a-d converter continues operating until the a-d conversion start flag is set to 0 by software. figure 2.8.11. operation timing of repeat sweep mode 0 item item set-up set-up operation clock f ad divided-by-4 f ad / divided- by-2 f ad / f ad 8-bit / 10-bit o resolution analog input pin an 0 and an 1 (2 pins) / an 0 to an 3 (4 pins) / an 0 to an 5 (6 pins) / an 0 to an 7 (8 pins) o o sample & hold not activated activated o (2) an1 conversion begins after an0 conversion is complete a-d conversion start flag ? ? a-d register 0 a-d register 1 f ad a-d register i result result result 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles (3) consecutive conversion a-d conversion is complete (1) start a-d conversion set to ??by software. cleared to ??by software note: when f ad frequency is less than 1mh z , sample and hold function cannot be selected. conversion rate per analog input pin is 49 f ad cycles for 8-bit resolution and 59 f ad cycles for 10-bit resolution. (4)
339 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.12. set-up procedure of repeat sweep mode 0 b7 b0 1 setting a-d conversion start flag a-d control register 0 [address 03d6 16 ] adcon0 a-d conversion start flag 1 : a-d conversion started transmitting conversion result to a-d register i eight low-order bits of a-d conversion result b7 b0 (b15) (b8) b7 b0 a-d register 0 [address 03c1 16 , 03c0 16 ] ad0 a-d register 1 [address 03c3 16 , 03c2 16 ] ad1 a-d register 2 [address 03c5 16 , 03c4 16 ] ad2 a-d register 3 [address 03c7 16 , 03c6 16 ] ad3 a-d register 4 [address 03c9 16 , 03c8 16 ] ad4 a-d register 5 [address 03cb 16 , 03ca 16 ] ad5 a-d register 6 [address 03cd 16 , 03cc 16 ] ad6 a-d register 7 [address 03cf 16 , 03ce 16 ] ad7 during 10-bit mode two high-order bits of a-d conversion result during 8-bit mode when read, the content is indeterminate start a-d conversion b7 b0 0 setting a-d conversion start flag a-d control register 0 [address 03d6 16 ] adcon0 a-d conversion start flag 0 : a-d conversion disabled stop a-d conversion b7 b0 selecting sample and hold a-d control register 2 [address 03d4 16 ] adcon2 a-d conversion method select bit 1 : with sample and hold b7 b0 setting a-d control register 0 and a-d control register 1 a-d control register 0 [address 03d6 16 ] adcon0 a-d sweep pin select bit (note) 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 b7 b0 a-d control register 1 [address 03d7 16 ] adcon1 a-d operation mode select bit 1 (note) 0 (must always be ??in repeat sweep mode 0) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected repeat sweep mode 0 is selected (note) nothing is arranged for this bit. fix ??to this bit. a-d conversion start flag 0 : a-d conversion disabled frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected 0 011 vref connect bit 1 : vref connected 00 0 1 invalid in repeat sweep mode 0 1 repeatedly carries out a-d conversion on pins selected through the a-d sweep pin select bit. note: rewrite to analog input pin select bit after changing a-d operation mode. nothing is arranged for these bits. fix ??to these bits.
340 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.8.6 operation of a-d converter (in repeat sweep mode 1) figure 2.8.14. operation timing of repeat sweep mode 1 in repeat sweep mode 1, choose functions from those listed in table 2.8.6. operations of the circled items are described below. figure 2.8.13 shows ani pin's sweep sequence, figure 2.8.14 shows timing chart, and figure 2.8.15 shows the set-up procedure. operation (1) setting the a-d conversion start flag to 1 causes the a-d converter to start the conversion on voltage input to the an 0 pin. (2) after the a-d conversion on voltage input to the an 0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to a-d register 0. (3) every time the a-d converter carries out a-d conversion on a selected analog input pin, the a-d converter carries out a-d conversion on only one unselected pin, and then the a-d converter carries out a-d conver- sion from the an 0 pin again. (see figure 2.8.13.) the conversion result is transmitted to a-d register i every time conversion on a pin is completed. the a-d conversion interrupt request bit does not go to 1. (4) the a-d converter continues operating until software goes the a-d convers ion start flag to 0. table 2.8.6. choosed functions figure 2.8.13. ani pin's sweep sequence in repeat sweep mode 1 item item set-up set-up operation clock f ad divided-by-4 f ad / divided- by-2 f ad / f ad 8-bit / 10-bit o resolution analog input pin an 0 (1 pin) / an 0 and an 1 (2 pins) / an 0 to an 2 (3 pins) / an 0 to an 3 (4 pins) o o sample & hold not activated activated o when an 0 is selected converted analog input pin time 0000000000 1 2 3 4 5 6 7 1 2 . . . when an 0 , an 1 are selected converted analog input pin time 0000000 1111111 2 3 4 5 6 7 . . . 0 2 converted analog input pin time 0000000 222222 3 4 5 6 7 . . . 3 111111 when an 0 to an 2 are selected converted analog input pin time 000000 3333 2 4 5 6 7 . . . 11111 2222 3 4 when an 0 to an 3 are selected a-d conversion start flag ? ? a-d register 0 a-d register 1 f ad a-d register 2 result result result set to ??by software result cleared to ??by software (2) (3) consecutive conversion 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles a-d conversion is complete (4) conversion result is transfered to a-d conversion register 0 note: when f ad frequency is less than 1mhz, sample and hold function cannot be selected. conversion rate per analog input pin is 49 f ad cycles for 8-bit resolution and 59 f ad cycles for 10-bit resolution. 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles 8-bit resolution : 28 f ad cycles 10-bit resolution : 33 f ad cycles 8-bit resolution : 28 ad cycles 10-bit resolution : 33 ad cycles (1) start an 0 pin conversion
341 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.15. set-up procedure of repeat sweep mode 1 b7 b0 setting a-d conversion start flag a-d control register 0 [address 03d6 16 ] adcon0 a-d conversion start flag 1 : a-d conversion started transmitting conversion result to a-d register i eight low-order bits of a-d conversion result b7 b0 (b15) (b8) b7 b0 a-d register 0 [address 03c1 16 , 03c0 16 ] ad0 a-d register 1 [address 03c3 16 , 03c2 16 ] ad1 a-d register 2 [address 03c5 16 , 03c4 16 ] ad2 a-d register 3 [address 03c7 16 , 03c6 16 ] ad3 a-d register 4 [address 03c9 16 , 03c8 16 ] ad4 a-d register 5 [address 03cb 16 , 03ca 16 ] ad5 a-d register 6 [address 03cd 16 , 03cc 16 ] ad6 a-d register 7 [address 03cf 16 , 03ce 16 ] ad7 during 10-bit mode two high-order bits of a-d conversion result during 8-bit mode when read, the content is indeterminate start a-d conversion b7 b0 0 setting a-d conversion start flag a-d control register 0 [address 03d6 16 ] adcon0 a-d conversion start flag 0 : a-d conversion disabled stop a-d conversion b7 b0 selecting sample and hold a-d control register 2 [address 03d4 16 ] adcon2 a-d conversion method select bit 1 : with sample and hold b7 b0 setting a-d control register 0 and a-d control register 1 a-d control register 0 [address 03d6 16 ] adcon0 a-d sweep pin select bit (note) 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 b7 b0 a-d control register 1 [address 03d7 16 ] adcon1 a-d operation mode select bit 1 (note) 0 (must always be ??in repeat sweep mode 1) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected repeat sweep mode 1 is selected (note) nothing is arranged for this bit. fix ??to this bit. a-d conversion start flag 0 : a-d conversion disabled frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected 0 011 vref connect bit 1 : vref connected 00 1 1 invalid in repeat sweep mode 1 1 converts non-selected pin after converting pins selected through the a-d sweep pin select bit. note: rewrite to analog input pin select bit after changing a-d operation mode. 1 nothing is arranged for these bits. fix ??to these bits.
342 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.8.7 precautions for a-d converter figure 2.8.16. use of capacitors to reduce noice (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped. in particular, when the vref connection bit is changed from 0 to 1, start a-d conversion after an elapse of 1 m s or longer. (2) to reduce conversion error due to noise, connect a voltage to the avcc pin and to the v ref pin from an independent source. it is recommended to connect a capacitor between the avss pin and the avcc pin, between the avss pin and the v ref pin, and between the avss pin and the analog input pin (ani). figure 2.8.16 shows an example of connecting the capacitors to these pins. (3) set the direction register of the the port corresponding to a pin to be used as an analog input pin to input. (4) rewrite to analog input pin after changing a-d operation mode. the two cannot be set at the same time. (5) when using the one-shot or single sweep mode confirm that a-d conversion is complete before reading the a-d register. (note: when a-d conversion interrupt request bit is set, it shows that a-d conversion is completed.) (6) when using the repeat mode or repeat sweep mode 0 or 1 use the undivided main clock as the internal cpu clock. av ss av cc v ref an i microcomputer c1 c2 c3 c1 3 0.47 m f, c2 3 0.47 m f, c3 3 100 pf (for reference) use thick and shortest possible wiring to connect capacitors. note 1: note 2: v cc
343 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) the a-d converter compares the reference voltage (vref) generated internally based on the contents of the successive comparison register with the analog input voltage (v in ) input from the analog input pin. each bit of the comparison result is stored in the successive comparison register until analog-to-digital conversion (successive comparison method) is complete. if a trigger occurs, the a-d converter carries out the following: 1. fixes bit 9 of the successive comparison register. compares vref with v in : [in this instance, the contents of the successive comparison register are 1000000000 2 (default).] bit 9 of the successive comparison register varies depending on the comparison re- sult as follows. if vref < v in , then 1 is assigned to bit 9. if vref > v in , then 0 is assigned to bit 9. 2. fixes bit 8 of the successive comparison register. sets bit 8 of the successive comparison register to 1, then compares vref with v in . bit 8 of the successive comparison register varies depending on the comparison result as follows: if vref < v in , then 1 is assigned to bit 8. if vref > v in , then 0 is assigned to bit 8. 3. fixes bit 7 through bit 0 of the successive comparison register. carries out step 2 above on bit 7 through bit 0. after bit 0 is fixed, the contents of the successive comparison register (conversion result) are transmitted to a-d register i. vref is generated based on the latest content of the successive comparison register. table 2.8.7 shows the relationship of the successive comparison register contents and vref. table 2.8.8 shows how the successive comparison register and vref vary while a-d conversion is in progress. figure 2.8.17 shows theoretical a-d conversion characteristics. 2.8.8 method of a-d conversion (10-bit mode) table 2.8.7. relationship of the successive comparison register contents and vref successive approximation register : n vref (v) x 1024 v ref 2048 v ref n 00 1 to1023
344 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.8.17. theoretical a-d conversion characteristics (10-bit mode) table 2.8.8. variation of the successive comparison register and vref while a-d conversion is in progress (10-bit mode) 1 1 n 9 000000000 000000000 100000000 n 9 n 8 10000000 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 0 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 n 0 b9 b0 1st comparison result 2nd comparison result successive approximation register v ref change a-d converter stopped 1st comparison 2nd comparison 3rd comparison 10th comparison conversion complete v ref 2 v ref 4 v ref 8 v ref ...... v ref 1024 2048 v ref [v] 2 [v] 2 v ref 2048 v ref [v] 2 v ref 4 v ref 8 v ref 2048 v ref [v] 4 n 9 = 1 + n 9 = 0 n 8 = 1 + 8 v ref n 8 = 0 2 v ref 4 v ref 2048 v ref [v] 4 v ref v ref 8 v ref this data transfers to the bit 0 to bit 9 of a-d register. 000 16 001 16 002 16 003 16 3fe 16 3ff 16 result of a-d conversion analog input voltage v ref 1024 x 1 v ref 1024 x 2 v ref 1024 x 3 x 1021 v ref 1024 v ref 1024 x 1022 v ref 1024 x 1023 v ref v ref 1024 x 0.5 theoretical a-d conversion characteristic ideal a-d conversion characteristic 0
345 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (1) in 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes a-d conversion result. hence, if compared to a result obtained by using an 8-bit a-d converter, the voltage compared is different by 3 v ref /2048 (see what are underscored in table 2.8.9), and differences in stepping points of output codes occur as shown in figure 2.8.18. 2.8.9 method of a-d conversion (8-bit mode) figure 2.8.18. the level conversion characteristics of 8-bit mode and 8-bit a-d converter table 2.8.9. the comparison voltage in 8-bit mode compared to 8-bit a-d converter comparison voltage vref 8-bit mode 8-bit a-d converter 2 8 v ref 2 10 v ref n x 0.5 x 2 8 v ref 2 8 v ref n x 0.5 n = 0 n = 1 to 255 00 x 07 05 06 03 00 02 analog input voltage (mv) output code (result of a-d conversion) 02 01 00 analog input voltage (mv) output code (result of a-d conversion) 04 02 01 00 01 10-bit mode 8-bit mode 8bit-mode 10bit-mode 08 09 10 30 17.5 37.5 (note) optimal conversion characteristics of 8-bit a-d converter (v ref = 5.12 v) optimal conversion characteristics in 8-bit mode (v ref = 5.12 v) note: differences in stepping points of output code for analog input voltage.
346 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 2.8.10. variation of the successive comparison register and vref while a-d conversion is in progress (8-bit mode) figure 2.8.19. theoretical a-d conversion characteristics (8-bit mode) 1 1 n 9 000000000 000000000 100000000 n 9 n 8 10000000 n 9 n 8 n 7 n 6 n 5 n 4 n 3 10 0 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 00 b9 b0 1st comparison result 2nd comparison result successive approximation register v ref change a-d converter stopped 1st comparison 2nd comparison 3rd comparison 8th comparison conversion complete 2 v ref 4 v ref 8 v ref ...... v ref 256 2048 v ref [v] 2 v ref [v] 2 v ref 2048 v ref [v] 2 v ref 4 v ref 2048 v ref [v] 2 v ref 4 v ref 8 v ref 2048 v ref [v] 4 4 v ref n 9 = 1 + v ref n 9 = 0 8 v ref n 8 = 1 + 8 v ref n 8 = 0 this data transfers to bit 0 to bit 7 of a-d register. 00 16 01 16 02 16 03 16 fe 16 ff 16 result of a-d conversion analog input voltage x 2 v ref 256 v ref 256 x 3 x 4 v ref 256 v ref 256 x 254 v ref 256 x 255 v ref v ref 2048 x 3 theoretical a-d conversion characteristic of general 8-bit a-d converter 0 v ref 256 x 1 theoretical a-d conversion characteristic in the 8-bit mode
347 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.8.10 absolute accuracy and differential non-linearity error ?absolute accuracy absolute accuracy is the difference between output code based on the theoretical a-d conversion characteristics, and actual a-d conversion result. when measuring absolute accuracy, the voltage at the middle point of the width of analog input voltage (1-lsb width), that can meet the expectation of outputting an equal code based on the theoretical a-d conversion characteristics, is used as an ana- log input voltage. for example, if 10-bit resolution is used and if v ref (reference voltage) = 5.12 v, then 1-lsb width becomes 5 mv, and 0 mv, 5 mv, 10 mv, 15 mv, 20 mv, are used as analog input voltages. if analog input voltage is 25 mv, absolute accuracy = 3lsb refers to the fact that actual a-d conversion falls on a range from 002 16 to 008 16 though an output code, 005 16 , can be ex- pected from the theoretical a-d conversion characteristics. zero error and full-scale error are included in absolute accuracy. also, all the output codes for analog input voltage between v ref and avcc becomes 3ff 16 . figure 2.8.20. absolute accuracy (10-bit resolution) 000 16 001 16 002 16 003 16 004 16 005 16 006 16 0 analog input voltage (mv) theoretical a-d conversion characteristic 510152025303540455055 007 16 008 16 009 16 00a 16 00b 16 +3lsb ?lsb output code (result of a-d conversion)
348 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ?differential non-linearity error differential non-linearity error refers to the difference between 1-lsb width based on the theoretical a- d conversion characteristics (an analog input width that can meet the expectation of outputting an equal code) and an actually measured 1-lsb width (analog input voltage width that outputs an equal code). if 10-bit resolution is used and if v ref (reference voltage) = 5.12 v, differential non-linearity error = 1lsb refers to the fact that 1-lsb width actually measured falls on a range from 0 mv to 10 mv though 1-lsb width based on the theoretical a-d conversion characteristics is 5 mv (see 5.2 a-d converter's standard characteristics). figure 2.8.21. differential non-linearity error (10-bit resolution) 000 16 001 16 002 16 003 16 004 16 005 16 006 16 0 analog input voltage (mv) differential non-linear error 5 101520 253035 4045 007 16 008 16 009 16 output code (result of a-d conversion) 1lsb width for theoretical a-d conversion characteristic
349 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.8.11 internal equivalent circuit of analog input figure 2.8.22 shows the internal equivalent circuit of analog input. figure 2.8.22. internal equivalent circuit to analog input on resistor approx. 2k w a-d successive conversion register analog input voltage avcc avss chopper-type amplifier a-d conversion interrupt request vcc vss v in a-d control register 0 comparison voltage comparison reference voltage (vref) generator v ref avss vref b2 b1 b0 vcc vss an i wiring resistor approx. 0.2k w on resistor approx. 0.6k w sw2 sampling control signal sw1 c = approx. 3.0pf sw3 sw4 amp on resistor, approx. 5k w sw2 reference control signal resistor ladder control signal for sw2 control signal for sw3 connect to connect to comparison connect to connect to sampling i ladder-type switches i ladder-type wiring resistors on resistor approx. 0.6k w an0 parasitic diode sw1 sw1 conducts only on the ports selected for analog input. sw2 and sw3 are open when a-d conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. sw4 conducts only when a-d conversion is not in progress. parasitic diode warning: use only as a standard for designing this data. mass production may cause some changes in device characteristics. (i = 8) (i = 8)
350 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r to carry out a-d conversion properly, charging the internal capacitor c shown in figure 2.8.23 has to be completed within a specified period of time. with t as the specified time, time t is the time that switches sw2 and sw3 are connected to o in figure 2.8.22. let output impedance of sensor equivalent circuit be r0, microcomputers internal resistance be r, precision (error) of the a-d converter be x, and the a-d converters resolution be y. vc is generally v c = v in {1 C e } and when t = t, v c =v in C v in =v in (1 C ) e = C =ln hence, r0 = C C r each value is r = 7.8 k w , c = 3 pf, t = 0.3 us in the a-d conversion mode with sample & hold. for example, when the a-d converters resolution is 10 bits and precision (error) of the a-d converter is 0.1 lsb, y = 10, x = 0.1lsb. hence, r0 = C C7.8 x10 3 3.0 x 10 3 2.8.12 sensors output impedance under a-d conversion thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the a-d con- verter turns out to be approximately 3.0 k w . tables 2.8.11 and 2.8.12 show output impedance values based on the lsb values. figure 2.8.23 a circuit equivalent to the a-d conversion terminal c (r0 +r) t c (r0 + r) t C c (r0 + r) t C y x y x y x y x c ? ln t y x 3.0 x 10 C12 ? ln 1024 0.1 0.3 x 10 -6 v c c (3.0pf) v in microprocessor's inside sensor-equivalent circuit r (7.8kw) r 0
351 a-d converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 2.8.11. output impedance values based on the lsb values (1) table 2.8.12. output impedance values based on the lsb values (2) f(x in ) (mhz) cycle ( m s) sampling time ( m s) r (kohm) c (pf) accuracy (lsb) r0 (kohm) 10 0.1 0.3 (3 5 cycle, sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 3.0 4.5 5.3 5.9 6.4 6.8 7.2 7.5 7.8 8.1 10 0.1 0.2 (2 5 cycle, sample & hold bit is disabled) 7.8 3.0 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.4 0.9 1.3 1.7 2.0 2.2 2.4 2.6 2.8 f(x in ) (mhz) cycle ( m s) sampling time ( m s) r (kohm) c (pf) accuracy (lsb) r0 (kohm) 10 0.1 0.3 (3 5 cycle, sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 4.9 7.0 8.2 9.1 9.9 10.5 11.1 11.7 12.1 12.6 10 0.1 0.2 (2 5 cycle, sample & hold bit is disabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.7 2.1 2.9 3.5 4.0 4.4 4.8 5.2 5.5 5.8
352 d-a converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.9 d-a converter figure 2.9.2. d-a converter-related registers figure 2.9.1. memory map of d-a converter-related registers 2.9.1 overview the d-a converter used in the M30218 group is based on the 8-bit r-2r technique. (1) output voltage the d-a converter outputs voltage within a range from 0 v to v ref . the output voltage is determined by v ref /(256) x the d-a register contents. the d-a converter is not effected by the vref connection bit of the a-d converter. (2) conversion time tsu = 3 m s (3) output from the d-a converter and the direction register to use the d-a converter, do not set the direction register of the relevant port to output. (4) pins related to the d-a converter ? da 0 pin, da 1 pin output pins of the d-a converter ? avcc pin the power source pin of the analog section ? v ref pin input pin of the reference voltage ? avss pin the gnd pin of the analog section (5) registers related to the d-a converter figure 2.9.1 shows the memory map of d-a converter-related registers, and figure 2.9.2 shows d-a converter-related registers. (6) note d-a output pins shared with p9 7 and p9 6 . the two pins are input ports and floating at the reset. 03d8 16 03d9 16 03da 16 03db 16 03dc 16 d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? d-a register symbol address when reset dai (i = 0,1) 03d8 16 , 03da 16 indeterminate w r b7 b0 function r w output value of d-a conversion
353 d-a converter m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r the following is the d-a converter operation. figure 2.9.3 shows the set-up procedure. 2.9.2 d-a converter operation (1) writing a value to the d-a register i starts d-a conversion. (2) setting the d-ai output enable bit to 1 outputs an analog signal on the dai pin. (3) the d-a converter continues outputting an analog signal until the d-a output enable bit is set to 0. operation figure 2.9.3. set-up procedure of d-a converter setting d-a register d-a register 0 [address 03d8 16 ] da0 d-a register 1 [address 03da 16 ] da1 output value of d-a conversion b7 b0 d-a0 output enable bit 1 : output enabled setting d-a control register d-a control register [address 03dc 16 ] dacon b7 b0 d-a1 output enable bit 1 : output enabled
354 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.10 dmac 2.10.1 overview dmac transfers one data item held in the source address to the destination address every time a transfer request is generated. the following is a dmac overview. (1) source address and destination address both the register which indicates a source and the register which indicates a destination comprise of 24 bits, so that each can cover a 1m bytes space. after transfer of one bit of data is completed, the address in either the source register or the destination register can be incremented. however, both registers cannot be incremented. the links between the source and destination are as follows: (a) a fixed address from an arbitrary 1m bytes space (b) an arbitrary 1m bytes space from a fixed address (c) a fixed address from another fixed address (2) the number of bits of data transferred the number of bit of data indicated by the transfer counter is transferred. if a 16-bit transfer is se- lected, up to 128 k bytes can be transferred. if an 8-bit transfer is selected, up to 64k bytes can be transferred. the transfer counter is decremented each time one bit of data is transferred, and a dma interrupt occurs when the transfer counter underflows. (3) dma transfer factor ________ ________ the dma transfer factor can be selected from the following 15 factors: falling edge of int0/int1 pin, timer a0 interrupt request through timer a4 interrupt request, timer b0 interrupt request through timer b2 interrupt request, uart0 transmission interrupt request, uart0 reception interrupt request, uart1 transmission interrupt request, uart1 reception interrupt request, a-d conversion interrupt request, and software trigger. when software trigger is selected, dma transfer is generated by writing 1 to software dma interrupt request bit. when other factor is selected, dma transfer is generated by generating corresponding interrupt request. (4) channel priority if dma0 transfer request and dma1 transfer request occur simultaneously, priority is given to dma0. (5) writing to a register when writing to the source register or the destination register with dma enabled, the content of the register with a fixed address will change at the time of writing. therefore, the user should not write to a register with a fixed address when the dma enable bit is set to 1. the contents of the register with forward direction selected, and the transfer counter, are changed when reloaded. a reload occurs either when the transfer counter underflows, or when the dma enable bit is re-enabled, after having been disabled. the reload register can be written to, as in normal conditions. (6) reading to a register the reload register can be read to, as in normal conditions.
355 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (7) switching function (a) switching between one-shot transfer and repeated transfer 'one-shot transfer' refers to a mode in which dma is disabled after the transfer counter underflows. 'repeated transfer' refers to a mode in which a reload is carried out after the transfer counter underflows. the reload is carried out for the transfer counter and on the address pointer subjected to forward direction. the following are examples of operation in which the options listed are selected. ? a fixed address from an arbitrary 1m byte space, one-shot transfer ........................................ p358 ? an arbitrary 1m byte space from a fixed address, repeated transfer ........................................ p360 (8) registers related to dmac figure 2.10.1 shows the memory map of dmac-related registers, and figures 2.10.2 and 2.10.3 show dmac-related registers. figure 2.10.1. memory map of dmac-related registers 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002c 15 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003c 16 004b 16 004c 16 03b8 16 03b9 16 03ba 16 dma0 control register (dm0con) dma0 source pointer (sar0) dma0 transfer counter (tcr0) dma0 destination pointer (dar0) dma1 control register (dm1con) dma1 source pointer (sar1) dma1 transfer counter (tcr1) dma1 destination pointer (dar1) dma0 cause select register (dm0sl) dma1 cause select register (dm1sl) dma0 interrupt control register (dm0ic) dma1 interrupt control register (dm1ic)
356 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.10.2. dmac-related registers (1) d m a i r e q u e s t c a u s e s e l e c t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t d m i s l ( i = 0 , 1 )0 3 b 8 1 6 , 0 3 b a 1 6 0 0 1 6 b i t n a m e f u n c t i o n r b i t s y m b o l w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d m a r e q u e s t c a u s e s e l e c t b i t d s e l 0 d s e l 1 d s e l 2 d s e l 3 s o f t w a r e d m a r e q u e s t b i t i f s o f t w a r e t r i g g e r i s s e l e c t e d , a d m a r e q u e s t i s g e n e r a t e d b y s e t t i n g t h i s b i t t o 1 ( w h e n r e a d , t h e v a l u e o f t h i s b i t i s a l w a y s 0 ) d s r d m a i c o n t r o l r e g i s t e r s y m b o la d d r e s sw h e n r e s e t d m i c o n ( i = 0 , 1 )0 0 2 c 1 6 , 0 0 3 c 1 6 0 0 0 0 0 x 0 0 2 b i t n a m e f u n c t i o n b i t s y m b o l r w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t r a n s f e r u n i t b i t s e l e c t b i t 0 : 1 6 b i t s 1 : 8 b i t s d m b i t d m a s l d m a s d m a e r e p e a t t r a n s f e r m o d e s e l e c t b i t 0 : s i n g l e t r a n s f e r 1 : r e p e a t t r a n s f e r d m a r e q u e s t b i t ( n o t e 1 ) 0 : d m a n o t r e q u e s t e d 1 : d m a r e q u e s t e d 0 : d i s a b l e d 1 : e n a b l e d 0 : f i x e d 1 : f o r w a r d d m a e n a b l e b i t s o u r c e a d d r e s s d i r e c t i o n s e l e c t b i t ( n o t e 3 ) d e s t i n a t i o n a d d r e s s d i r e c t i o n s e l e c t b i t ( n o t e 3 ) 0 : f i x e d 1 : f o r w a r d d s d d a d n o t e 1 : d m a r e q u e s t c a n b e c l e a r e d b y r e s e t t i n g t h e b i t . n o t e 2 : t h i s b i t c a n o n l y b e s e t t o 0 . n o t e 3 : s o u r c e a d d r e s s d i r e c t i o n s e l e c t b i t a n d d e s t i n a t i o n a d d r e s s d i r e c t i o n s e l e c t b i t c a n n o t b e s e t t o 1 s i m u l t a n e o u s l y . b 3 b 2 b 1 b 0 0 0 0 0 : f a l l i n g e d g e o f i n t 0 / i n t 1 p i n ( n o t e ) 0 0 0 1 : s o f t w a r e t r i g g e r 0 0 1 0 : t i m e r a 0 0 0 1 1 : t i m e r a 1 0 1 0 0 : t i m e r a 2 0 1 0 1 : t i m e r a 3 0 1 1 0 : t i m e r a 4 0 1 1 1 : t i m e r b 0 1 0 0 0 : t i m e r b 1 1 0 0 1 : t i m e r b 2 1 0 1 0 : u a r t 0 t r a n s m i t 1 0 1 1 : u a r t 0 r e c e i v e 1 1 0 0 : u a r t 1 t r a n s m i t 1 1 0 1 : u a r t 1 r e c e i v e 1 1 1 0 : a - d c o n v e r s i o n 1 1 1 1 : i n h i b i t e d n o t e : a d d r e s s 0 3 b 8 1 6 i s f o r i n t 0 ; a d d r e s s 0 3 b a 1 6 i s f o r i n t 1 . ( n o t e 2 ) n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 .
357 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.10.3. dmac-related registers (2) b7 b0 b7 b0 (b8) (b15) function rw ?transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw ?source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw ?destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? a a a a a a
358 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in one-shot transfer mode, choose functions from the items shown in table 2.10.1. operations of the circled items are described below. figure 2.10.4 shows an example of operation and figure 2.10.5 shows the set-up procedure. 2.10.2 operation of dmac (one-shot transfer mode) figure 2.10.4. example of operation of one-shot transfer mode table 2.10.1. choosed functions operation (1) when software trigger is selected, setting software dma request bit to 1 generates a dma transfer request signal. (2) if dmac is active, data transfer starts, and the contents of the address indicated by the dmai forward-direction address pointer are transferred to the address indicated by the dmai desti- nation pointer. when data transfer starts directly after dmac becomes active, the value of the dmai transfer counter reload register is reloaded to the dmai transfer counter, and the value of the dmai source pointer is reloaded by the dmai forward-direction address pointer. each time a dma transfer request signal is generated, 1 byte of data is transferred. the dmai transfer counter is down counted, and the dmai forward-direction address pointer is up counted. (3) if the dma transfer counter underflows, the dma enable bit changes to 0 and dma transfer is completed. the dma interrupt request bit changes to 1 simultaneously. item transfer space unit of transfer set-up o o fixed address from an arbitrary 1 m bytes space arbitrary 1 m bytes space from a fixed address fixed address from fixed address 8 bits 16 bits dummy cycle source source dummy cycle dummy cycle bclk address bus rd signal wr signal data bus dmai request bit dma transfer counter dmai interrupt request bit dmai enable bit write signal to software dmai request bit cpu use source source dummy cycle indeterminate 00 16 ?in the case in which the number of transfer times is set to 2. (1) request signal for a dma transfer occurs cleared to ??when interrupt request is accepted, or cleared by software (2) data transfer begins cpu use cpu use ff 16 (3) underflow cpu use cpu use cpu use destination destination destination destination 01 16
359 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.10.5. set-up procedure of one-shot transfer mode when software dma request bit = ?? setting dmai request cause select register dmai request cause select register (i = 0, 1) [address 03b8 16 , 03ba 16 ] dmisl(i = 0, 1) dma request cause select bit 0 0 0 1 : software trigger b3 b2 b1 b0 b7 b0 01 0 0 0 software dma request bit set to ? setting dmai control register dmai control register (i = 0, 1) [address 002c 16 , 003c 16 ] dmicon(i = 0, 1) transfer unit bit select bit 1 : 8 bits repeat transfer mode select bit 0 : single transfer dma request bit 0 : dma not requested dma enable bit 0 : disabled source address direction select bit 1 : forward (bit 4 and bit 5 cannot be set to ??simultaneously) destination address direction select bit 0 : fixed (bit 4 and bit 5 cannot be set to ??simultaneously) b7 b0 01 0 0 01 setting dmai source pointer source pointer stores the source address b7 b0 (b15) (b8) b7 b0 b7 b0 (b16) (b23) dma0 source pointer [address 0022 16 to 0020 16 ] sar0 dma1 source pointer [address 0032 16 to 0030 16 ] sar1 b3 (b19) setting dmai destination pointer destination pointer stores the destination address b7 b0 (b15) (b8) b7 b0 b7 b0 (b16) (b23) dma0 destination pointer [address 0026 16 to 0024 16 ] dar0 dma1 destination pointer [address 0036 16 to 0034 16 ] dar1 b3 (b19) setting dmai transfer counter transfer counter set a value one less than the transfer count b0 (b8) b7 b0 dma0 transfer counter [address 0029 16 , 0028 16 ] tcr0 dma1 transfer counter [address 0039 16 , 0038 16 ] tcr1 b0 (b15) setting dmai control register dmai control register (i = 0, 1) [address 002c 16 , 003c 16 ] dmicon(i = 0, 1) dma enable bit 1 : enabled b7 b0 1 note: clear dma request bit simultaneously again. start dma transmission
360 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in repeat transfer mode, choose functions from the items shown in table 2.10.2. operations of the circled items are described below. figure 2.10.6 shows an example of operation and figure 2.10.7 shows the set-up procedure. 2.10.3 operation of dmac (repeated transfer mode) figure 2.10.6. example of operation of repeated transfer mode table 2.10.2. choosed functions (1) when software trigger is selected, setting software dma request bit to 1 generates a dma transfer request signal. (2) if dmac is active, data transfer starts, and the contents of the address indicated by the dmai forward-direction address pointer are transferred to the address indicated by the dmai desti- nation pointer. when data transfer starts directly after dmac becomes active, the value of the dmai transfer counter reload register is reloaded to the dmai transfer counter, and the value of the dmai source pointer is reloaded by the dmai forward-direction address pointer. each time a dma transfer request signal is generated, 2 byte of data is transferred. the dmai transfer counter is down counted, and the dmai forward-direction address pointer is up counted. (3) though dmai transfer counter is underflowed, dma enable bit is still 1. the dma interrupt request bit changes to 1 simultaneously. (4) after dmai transfer counter is underflowed, when the next dma request is generated, dma transfer is repeated from (1). operation o item transfer space unit of transfer set-up o fixed address from an arbitrary 1 m bytes space arbitrary 1 m bytes space from a fixed address fixed address from fixed address 8 bits 16 bits source source source bclk dmai request bit dma transfer counter dmai interrupt request bit dmai enable bit ?in the case in which the number of transfer times is set to 2. rd signal wr signal address bus data bus ? write signal to software dmai request bit source indeterminate 00 16 dummy cycle cpu use cpu use (3) underflow ff 16 cpu use source cpu use cleared to ??when interrupt request is accepted, or cleared by software cpu use cpu use 00 16 cpu use source cpu use destination 01 16 01 16 destination destination dummy cycle destination dummy cycle destination dummy cycle dummy cycle destination dummy cycle (1) request signal for a dma transfer occurs (2) data transfer begins
361 dmac m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.10.7. set-up procedure of repeated transfer mode when software dma request bit = ?? setting dmai request cause select register dmai request cause select register (i = 0, 1) [address 03b8 16 , 03ba 16 ] dmisl(i = 0, 1) b7 b0 01 0 0 0 software dma request bit set to ? setting dmai control register dmai control register (i = 0, 1) [address 002c 16 , 003c 16 ] dmicon(i = 0, 1) transfer unit bit select bit 0 : 16 bits repeat transfer mode select bit 1 : repeat transfer dma request bit 0 : dma not requested dma enable bit 0 : disabled source address direction select bit 0 : fixed (bit 4 and bit 5 cannot be set to ??simultaneously) destination address direction select bit 1 : forward (bit 4 and bit 5 cannot be set to ??simultaneously) b7 b0 10 0 0 10 setting dmai source pointer source pointer stores the source address b7 b0 (b15) (b8) b7 b0 b7 b0 (b16) (b23) dma0 source pointer [address 0022 16 to 0020 16 ] sar0 dma1 source pointer [address 0032 16 to 0030 16 ] sar1 b3 (b19) setting dmai destination pointer destination pointer stores the destination address b7 b0 (b15) (b8) b7 b0 b7 b0 (b16) (b23) dma0 destination pointer [address 0026 16 to 0024 16 ] dar0 dma1 destination pointer [address 0036 16 to 0034 16 ] dar1 b3 (b19) setting dmai transfer counter transfer counter set a value one less than the transfer count b0 b7 b0 dma0 transfer counter [address 0029 16 , 0028 16 ] tcr0 dma1 transfer counter [address 0039 16 , 0038 16 ] tcr1 b0 (b15) setting dmai control register dmai control register (i = 0, 1) [address 002c 16 , 003c 16 ] dmicon(i = 0, 1) dma enable bit 1 : enabled b7 b0 1 note: clear dma request bit simultaneously again. dma request cause select bit 0 0 0 1 : software trigger b3 b2 b1 b0 start dma transmission (b8)
362 crc calculation circuit m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.11.1 overview cyclic redundancy check (crc) is a method that compares crc code formed from transmission data by use of a polynomial generation with crc check data so as to detect errors in transmission data. using the crc calculation circuit allows generation of crc code. a polynomial counter is used for the polyno- mial generation. (1) registers related to crc calculation circuit figure 2.11.1 shows the memory map of crc-related registers, and figure 2.11.2 shows crc- re- lated registers. 2.11 crc calculation circuit figure 2.11.1. memory map of crc-related registers figure 2.11.2. crc-related registers 03bc 16 03bd 16 03be 16 crc data register (crcd) crc input register (crcin) s y m b o la d d r e s sw h e n r e s e t c r c d0 3 b d 1 6 , 0 3 b c 1 6 i n d e t e r m i n a t e b 7b 0b 7b 0 ( b 1 5 )( b 8 ) c r c d a t a r e g i s t e r w r c r c c a l c u l a t i o n r e s u l t o u t p u t r e g i s t e r f u n c t i o n v a l u e s t h a t c a n b e s e t 0 0 0 0 1 6 t o f f f f 1 6 s y m b oa d d r e s sw h e n r e s e t c r c i n0 3 b e 1 6 i n d e t e r m i n a t e b 7b 0 c r c i n p u t r e g i s t e r w r d a t a i n p u t r e g i s t e r f u n c t i o n v a l u e s t h a t c a n b e s e t 0 0 1 6 t o f f 1 6
363 crc calculation circuit m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.11.2 operation of crc calculation circuit the following describes the operation of the crc calculation. figure 2.11.3 shows an example of calcu- lation data 0123 16 using the crc calculation circuit. operation (1) the crc calculation circuit sets an initial value in the crc data register. (2) writing 1 byte data to the crc input register generates crc code based on the data register. crc code generation for 1 byte data finishes in two machine cycles. (3) the crc calculation circuit detects an error by means of comparing the crc-checking data with the content of the crc data register, after the next data is written to the crc input register. (4) the content of crc data register after all data is written becomes crc code. figure 2.11.3. calculation example using the crc calculation circuit b15 b0 (1) setting 0000 16 crc data register crcd [03bd 16 , 03bc 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [03be 16 ] 2 cycles after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [03be 16 ] after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m16c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1
364 watchdog timer m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.12.1 overview the watchdog timer can detect a runaway program using its 15-bit timer prescaler. the following is an overview of the watchdog timer. (1) watchdog timer start procedure when reset, the watchdog timer is in stopped state. writing to the watchdog timer start register initializes the watchdog timer to 7fff 16 and causes it to start performing a down count. the watchdog timer, once started operating, cannot be stopped by any means other than stopping conditions. (2) watchdog timer stop conditions the watchdog timer stops in any one of the following states: (a) period in which the cpu is in stopped state (b) period in which the cpu is in waiting state (c) period in which the microcomputer is in hold state (3) watchdog timer initialization the watchdog timer is initialized to 7fff 16 in the cases given below, and begins a down count. (a) when the watchdog timer writes to the watchdog timer start register while a count is in progress (b) when the watchdog timer underflows (4) runaway detection when the watchdog timer underflows, a watchdog timer interrupt occurs. in writing a program, write to the watchdog timer start register before the watchdog timer underflows. the watchdog timer interrupt occurs regardless of the status of the interrupt enable flag (i flag). in processing a watchdog timer interrupt, set the software reset bit to 1 to reset software. (5) watchdog timer cycle the watchdog timer cycle varies depending on the bclk and the frequency division ratio of the prescaler selected. 2.12 watchdog timer table 2.12.1. the watchdog timer cycle cm07 cm06 cm17 cm16 bclk wdc7 period 0 0 0 0 0 1 0 0 0 10mhz 0 0 1 5mhz 0 1 0 2.5mhz 0 1 1 0.625mhz 1 invalid invalid 1.25mhz invalid invalid invalid 32khz 0 1 0 1 0 1 0 1 0 1 invalid approx. 52.4ms (note) approx. 419.4ms (note) approx. 104.9ms (note) approx. 838.9ms (note) approx. 209.7ms (note) approx. 1.68s (note) approx. 838.9ms (note) approx. 6.71s (note) approx. 419.4ms (note) approx. 3.36s (note) approx. 2s (note) note: an error due to the prescaler occurs.
365 watchdog timer m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.12.1. memory map of watchdog timer-related registers figure 2.12.2. watchdog timer-related registers (6) registers related to the watchdog timer figure 2.12.1 shows the memory map of watchdog timer-related registers, and figure 2.12.2 shows watchdog timer-related registers. 000e 16 000f 16 watchdog timer start register (wdts) watchdog timer control register (wdc) watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 regardless of whatever value is written. reserved bit reserved bit must always be set to ? must always be set to ? 0 0 aa aa aa aa a a aa a aa a a a
366 watchdog timer m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.12.2 operation of watchdog timer the following is an operation of the watchdog timer. figure 2.12.3 shows the operation timing, and figure 2.12.4 shows the set-up procedure. (1) writing to the watchdog timer start register initializes the watchdog timer to 7fff 16 and causes it to start a down count. (2) with a count in progress, writing to the watchdog timer start register again initializes the watchdog timer to 7fff 16 and causes it to resume counting. (3) either executing the wait instruction or going to the stopped state causes the watchdog timer to hold the count in progress and to stop counting. the watchdog timer resumes count- ing after returning from the execution of the wait instruction or from the stopped state. (4) if the watchdog timer underflows, it is initialized to 7fff 16 and continues counting. at this time, a watchdog timer interrupt occurs. operation figure 2.12.3. operation timing of watchdog timer (1) start count write signal to the watchdog timer start register 7fff 16 0000 16 ? ? (4) generate watchdog timer interrupt (2) write operation (3) in stopped state, or wait instruction is executing, etc
367 watchdog timer m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.12.4. set-up procedure of watchdog timer reserved bit must always be ?? watchdog timer control register [address 000f 16 ] wdc setting watchdog timer control register b7 b0 setting watchdog timer start register the watchdog timer is initialized and starts counting with a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 ? regardless of the value written. watchdog timer start register [address 000e 16 ] wdts b0 b7 software reset software reset bit the device is reset when this bit is set to ?? the value of this bit is ??when read. processor mode register 0 [address 0004 16 ] pm0 b7 b0 1 generating watchdog timer interrupt 00 prescaler select bit 0 : divided by 16 1 : divided by 128
368 address match interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.13.1 overview the address match interrupt is used for correcting a rom or for a simplified debugging-purpose monitor. the following is an overview of the address match interrupt. (1) enabling/disabling the address match interrupt the address match interrupt enable bit can be used to enable and disable an address match interrupt. it is affected neither by the processor interrupt priority level (ipl) nor the interrupt enable flag (i flag). (2) timing of the address match interrupt an interrupt occurs immediately before executing the instruction in the address indicated by the ad- dress match interrupt register. set the first address of the instruction in the address match interrupt register. setting a half address of an instruction or an address of tabulated data does not generate an address match interrupt. the first instruction of an interrupt routine does not generate an address match interrupt either. (3) returning from an address match interrupt the return address put in the stack when an address match interrupt occurs depends on the instruc- tion not yet executed (the instruction the address match interrupt register indicates). the return ad- dress is not put in the stack. for this reason, to return from an address match interrupt, either rewrite the content of the stack and use the reit instruction or use the pop instruction to restore the stack to the state as it was before the interrupt occurred and return by use of a jump instruction. figure 2.13.1 shows unexecuted instructions and corresponding the stacked addresses. 2.13 address match interrupt ? 16-bit operation code instructions ? 8-bit operation code instructions given below add.b:s #imm8,dest sub.b:s #imm8,dest and.b:s #imm8,dest or.b:s #imm8,dest mov.b:s #imm8,dest stz.b:s #imm8,dest stnz.b:s #imm8,dest stzx.b:s #imm81,#imm82,dest cmp.b:s #imm8,dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm,dest (however, dest = a0/a1) ? instructions other than those listed above figure 2.13.1. unexecuted instructions and corresponding stacked addresses (4) how to determine an address match interrupt address match interrupts can be set at two different locations. however, both location will have the same vector address. therefore, it is necessary to determine which interrupt has occurred; address match interrupt 0 or address match interrupt 1. using the content of the stack, etc., determine which interrupt has occurred according to the first part of the address match interrupt routine.
369 address match interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.13.2. memory map of address match interrupt-related registers (5) registers related to the address match interrupt figure 2.13.2 shows the memory map of address match interrupt-related registers, and figure 2.13.3 shows address match interrupt-related registers. figure 2.13.3. address match interrupt-related registers 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) address match interrupt enable register (aier) b i t n a m e b i t s y m b o l s y m b o la d d r e s s w h e n r e s e t a i e r0 0 0 9 1 6 x x x x x x 0 0 2 a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r f u n c t i o n w r a d d r e s s m a t c h i n t e r r u p t 0 e n a b l e b i t 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d a i e r 0 a d d r e s s m a t c h i n t e r r u p t 1 e n a b l e b i t a i e r 1 s y m b o la d d r e s s w h e n r e s e t r m a d 00 0 1 2 1 6 t o 0 0 1 0 1 6 x 0 0 0 0 0 1 6 r m a d 10 0 1 6 1 6 t o 0 0 1 4 1 6 x 0 0 0 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 w r a d d r e s s s e t t i n g r e g i s t e r f o r a d d r e s s m a t c h i n t e r r u p t f u n c t i o nv a l u e s t h a t c a n b e s e t a d d r e s s m a t c h i n t e r r u p t r e g i s t e r i ( i = 0 , 1 ) 0 0 0 0 0 1 6 t o f f f f f 1 6 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d b 0b 7b 0 b 3 ( b 1 9 )( b 1 6 ) b 7b 0 ( b 1 5 )( b 8 ) b 7 ( b 2 3 ) n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e .
370 address match interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.13.2 operation of address match interrupt the following is an operation of address match interrupt. figure 2.13.4 shows the set-up procedure of address match interrupt, and figure 2.13.5 shows the overview of the address match interrupt handling routine. operation (1) the address match interrupt handling routine sets an address to be used to cause the ad- dress match interrupt register to generate an interrupt. (2) setting the address match enable flag to 1 enables an interrupt to occur. (3) an address match interrupt occurs immediately before the instruction in the address indicated by the address match interrupt register as a program is executed. figure 2.13.4. set-up procedure of address match interrupt can be set to ?0000 16 ?to ?ffff 16 b7 b0 (b23) (b16) b7 b0 address match interrupt register 0 [address 0012 16 to 0010 16 ] rmad0 address match interrupt register 1 [address 0016 16 to 0014 16 ] rmad1 setting address match interrupt enable register address match interrupt enable register [address 0009 16 ] aier address match interrupt 0 enable bit 1: interrupt enabled b7 b0 setting address match interrupt register b7 b0 (b15) (b8) b4 (b20) b3 (b19) address match interrupt 1 enable bit 1: interrupt enabled
371 address match interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.13.5. overview of the address match interrupt handling routine address match interrupt routine [1] storing registers [2] determining the interrupt address address match 0? address match 0 program [3] rewriting the stack restoring registers reit no yes address match 1? address match 1 program no yes handling an error [1] storing the contents of the registers holding the main program status to be kept. [2] determining the interrupt address determining which factor generated the interrupt. [3] rewriting the stack rewriting the return address. explanation:
372 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.14 power control 2.14.1 overview power control refers to the reduction of cpu power consumption by stopping the cpu and oscillators, or decreasing the operation clock. the following is a description of the three available power control modes: (1) modes power control is available in three modes. (a) normal operation mode ? high-speed mode divide-by-1 frequency of the main clock becomes the bclk. the cpu operates with the bclk selected. each peripheral function operates according to its assigned clock. ? medium-speed mode divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the bclk selected. each peripheral function operates according to its assigned clock. ? low-speed mode fc becomes the bclk. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. each peripheral function operates according to its assigned clock. ? low power consumption mode the main clock operating in low-speed mode is stopped. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. the only peripheral functions that operate are those with the sub-clock selected as the count source. (b) wait mode the cpu operation is stopped. the oscillators do not stop. (c) stop mode all oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in decreasing power consumption. figure 2.14.1 shows the state transition diagram of the above modes.
373 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.14.1. state transition diagram of power control mode t r a n s i t i o n o f s t o p m o d e , w a i t m o d e t r a n s i t i o n o f n o r m a l m o d e r e s e t m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 8 m o d e ) i n t e r r u p t c m 1 0 = 1 a l l o s c i l l a t o r s s t o p p e dc p u o p e r a t i o n s t o p p e d m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 8 m o d e ) b c l k : f ( x i n ) / 8 c m 0 7 = 0 c m 0 6 = 1 l o w - s p e e d m o d e h i g h - s p e e d m o d e m a i n c l o c k i s o s c i l l a t i n g s u b c l o c k i s s t o p p e d m a i n c l o c k i s o s c i l l a t i n g s u b c l o c k i s s t o p p e d m a i n c l o c k i s s t o p p e d s u b c l o c k i s o s c i l l a t i n g m a i n c l o c k i s o s c i l l a t i n g s u b c l o c k i s o s c i l l a t i n g l o w p o w e r d i s s i p a t i o n m o d e h i g h - s p e e d / m e d i u m - s p e e d m o d e l o w - s p e e d / l o w p o w e r d i s s i p a t i o n m o d e n o r m a l m o d e s t o p m o d e s t o p m o d e s t o p m o d e a l l o s c i l l a t o r s s t o p p e d a l l o s c i l l a t o r s s t o p p e d w a i t m o d e w a i t m o d e w a i t m o d e c p u o p e r a t i o n s t o p p e d c p u o p e r a t i o n s t o p p e d i n t e r r u p t w a i t i n s t r u c t i o n i n t e r r u p t w a i t i n s t r u c t i o n i n t e r r u p t w a i t i n s t r u c t i o n c m 1 0 = 1 i n t e r r u p t i n t e r r u p t c m 1 0 = 1 b c l k : f ( x i n ) / 2 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 1 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 2 m o d e ) b c l k : f ( x i n ) / 1 6 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 1 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 1 6 m o d e ) b c l k : f ( x i n ) / 4 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 0 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 4 m o d e ) b c l k : f ( x i n ) c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 0 b c l k : f ( x i n ) / 8 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 8 m o d e ) c m 0 7 = 0 c m 0 6 = 1 h i g h - s p e e d m o d e b c l k : f ( x i n ) / 2 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 1 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 2 m o d e ) b c l k : f ( x i n ) / 1 6 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 1 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 1 6 m o d e ) b c l k : f ( x i n ) / 4 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 0 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 4 m o d e ) b c l k : f ( x i n ) c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 0 b c l k : f ( x c i n ) c m 0 7 = 1 b c l k : f ( x c i n ) c m 0 7 = 1 m a i n c l o c k i s o s c i l l a t i n g s u b c l o c k i s o s c i l l a t i n g c m 0 7 = 0 ( n o t e 1 , 3 ) c m 0 7 = 0 ( n o t e 1 ) c m 0 6 = 1 c m 0 4 = 0 c m 0 7 = 1 ( n o t e 2 ) c m 0 7 = 0 ( n o t e 1 ) c m 0 6 = 0 ( n o t e 3 ) c m 0 4 = 1 c m 0 7 = 1 ( n o t e 2 ) c m 0 5 = 1 c m 0 5 = 0 ? m 0 5 = 1 c m 0 4 = 0 ? m 0 4 = 1 c m 0 6 = 0 ( n o t e s 1 , 3 ) c m 0 6 = 1 c m 0 4 = 0 c m 0 4 = 1 ( n o t e s 1 , 3 ) n o t e 1 :s w i t c h c l o c k a f t e r o s c i l l a t i o n o f m a i n c l o c k i s s u f f i c i e n t l y s t a b l e . n o t e 2 :s w i t c h c l o c k a f t e r o s c i l l a t i o n o f s u b c l o c k i s s u f f i c i e n t l y s t a b l e . n o t e 3 :c h a n g e c m 0 6 a f t e r c h a n g i n g c m 1 7 a n d c m 1 6 . n o t e 4 :t r a n s i t i n a c c o r d a n c e w i t h a r r o w . ( r e f e r t o t h e f o l l o w i n g f o r t h e t r a n s i t i o n o f n o r m a l m o d e . )
374 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (2) switching the driving capacity of the oscillation circuit both the main clock and the secondary clock have the ability to switch the driving capacity. reducing the driving capacity after the oscillation stabilizes allows for further reduction in power consumption. (3) clearing stop mode and wait mode the stop mode and wait mode can be cleared by generating an interrupt request, or by resetting hardware. set the priority level of the interrupt to be used for clearing, higher than the processor interrupt priority level (ipl), and enable the interrupt enable flag (i flag). when an interrupt clears a mode, that interrupt is processed. table 2.14.1 shows the interrupts that can be used for clearing a stop mode and wait mode. (4) bclk in returning from wait mode or stop mode (a) returning from wait mode the processor immediately returns to the bclk, which was in use before entering wait mode. (b) returning from stop mode cm06 is set to 1 when the device enters stop mode after selecting the main clock for bclk. cm17, cm16, and cm07 do not change state. in this case, when restored from stop mode, the device starts operating in divided-by-8 mode. when the device enters stop mode after selecting the subclock for bclk, cm06, cm17, cm16, and cm07 all do not change state. in this case, when restored from stop mode, the device starts operat- ing in low-speed mode. table 2.14.1. interrupts available for clearing stop mode and wait mode can be used when an external clock in clock synchronous serial i/o mode is selected. can be used when the external signal is being counted in event counter mode. can be used in one-shot mode and one-shot sweep mode. note 1: note 2: note 3: cm02 = 0 impossible impossible note 3 possible possible possible possible possible possible possible possible possible possible possible possible possible possible possible possible possible possible possible possible impossible impossible impossible note 1 note 1 note 1 note 1 impossible impossible note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 possible possible possible possible possible possible dma0 interrupt dma1 interrupt a-d interrupt uart0 transmit interrupt uart0 receive interrupt uart1 transmit interrupt uart1 receive interrupt si/o automatic transfer interrupt fld interrupt timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt timer b0 interrupt timer b1 interrupt timer b2 interrupt int0 interrupt int1 interrupt int2 interrupt int3 interrupt int4 interrupt int5 interrupt wait mode interrupt for clearing stop mode cm02 = 1 impossible impossible impossible note 1 note 1 note 1 note 1 impossible impossible note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 possible possible possible possible possible possible
375 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (5) sequence of returning from stop mode sequence of returning from stop mode is oscillation start-up time and interrupt sequence. when interrupt is generated in stop mode, cm10 becomes 0 and clearing stop mode. starting oscillation and supplying bclk execute the interrupt sequence as follow: in the interrupt sequence, the processor carries out the following in sequence given: (a) cpu gets the interrupt information (the interrupt number and interrupt request level) by read- ing address 00000 16 . the interrupt request bit of the interrupt written in address 00000 16 will then be set to 0. (b) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (c) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer assignment flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (d) saves the content of the temporary register (note) within the cpu in the stack area. (e) saves the content of the program counter (pc) in the stack area. (f) sets the interrupt priority level of the accepted instruction in the ipl. note: this register cannot be utilized by the user. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. figure 2.14.2 shows the sequence of returning from stop mode. figure 2.14.2. sequence of returning from stop mode (6) registers related to power control figure 2.14.3 shows the memory map of power control-related registers, and figure 2.14.4 shows power control-related registers. address 00000 interrupt information bclk address bus data bus indeterminate sp-2 sp-4 vec vec+2 indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents pc writing ??to cm10 (all clock stop control bit) oscillation start-up stop mode interrupt sequence approximately 20 cycle (16 sec) (single-chip mode, f(x in ) = 10mhz) rd wr indeterminate operated by divided-by-8 mode inti shown above is the case where the main clock is selected for bclk. if the sub-clock is selected for bclk, the sub-clock functions as bclk when restored from stop mode, with the main clock's divide ratio unchanged. note:
376 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.14.4. power control-related registers figure 2.14.3. memory map of power control-related registers 0006 16 0007 16 system clock control register 0 (cm0) system clock control register 1 (cm1) system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p9 7 /da 0 0 1 : f c output 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit wait peripheral function clock stop bit 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 3, 4, 5) 0 : on 1 : off main clock division select bit 0 (note 7) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 6) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shifting to stop mode and at a reset. note 3: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to ?? when main clock oscillation is operating by itself, set system clock select bit (cm07) to ??before setting this bit to ?? note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 5: if this bit is set to ?? x out turns ?? the built-in feedback resistor remains being connected, so x in turns pulled up to x out (?? via the feedback resistor. note 6: set port xc select bit (cm04) to ??and stabilize the sub-clock oscillating before setting to this bit from ??to ? . do not write to both bits at the same time. and also, set the main clock stop bit (cm05) to ??and stabilize the main clock oscillating before setting this bit from ??to ?? note 7: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 8: f c32 is not included. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note4) 0 : clock on 1 : all clocks off (stop mode) note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is ?? if ?? division mode is fixed at 8. note 4: if this bit is set to ?? x out turns ?? and the built-in feedback resistor is cut off. x cin and x cout turn high- impedance state. cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r cm16 cm17 reserved bit always set to ? reserved bit always set to ? main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 0 reserved bit always set to ? reserved bit always set to ? 0 0
377 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.14.2 stop mode set-up (1) enables the interrupt used for returning from stop mode. (2) sets the interrupt enable flag (i flag) to 1. (3) clearing the protection and setting every-clock stop bit to 1 stops oscillation and causes the processor to go into stop mode. operation settings and operation for entering stop mode are described here. figure 2.14.5. example of stop mode set-up all clocks off (stop mode) b7 b0 (3) canceling protect protect register [address 000a 16 ] prcr 1 enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) 1 : write-enabled (3) all clocks off (stop mode) b7 b0 system clock control register 1 [address 0007 16 ] cm1 0000 reserved bit must be set to ?? all clock stop control bit 1 : all clocks off (stop mode) 1 interrupt control register sitic(i=0, 1) [address 0051 16 , 0053 16 ] siric(i=0, 1) [address 0052 16 , 0054 16 ] taiic(i=0 to 4) [address 0055 16 to 0059 16 ] tbiic(i=0 to 2) [address 005a 16 to 005c 16 ] (1) setting interrupt to cancel stop mode make sure that the interrupt priority level of the interrupt which is used to cancel the stop mode is higher than the processor interrupt priority(ipl). interrupt priority level select bit b7 b0 intiic(i=0 to 2) [address 005d 16 to 005f 16 ] intiic(i=3 to 5) [address 0047 16 to 0049 16 ] make sure that the interrupt priority level of the interrupt which is used to cancel the stop mode is higher than the processor interrupt priority(ipl). interrupt priority level select bit b7 b0 0 reserved bit must be set to ?? system clock control register 0 [address 0006 16 ] cm0 (3) setting operation clock after returning from stop mode on main clock (x in -x out ) stop bit b7 b0 system clock select bit x in , x out as this register becomes setting mentioned above when operating with x in (count source of bclk is x in ), the user does not need to set it again. 00 system clock control register 0 [address 0006 16 ] cm0 x cin -x cout generation port x c select bit b7 b0 system clock select bit x cin , x cout as this register becomes setting mentioned above when operating with x cin (count source of bclk is x cin ), the user does not need to set it again. when operating with x in , set port xc select bit to ??before setting system clock select bit to ?? the both bits cannot be set at the same time. 1 1 (when operating with x cin after returning) (when operating with x in after returning) (2) interrupt enable flag (i flag) ?
378 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.14.3 wait mode set-up figure 2.14.6. example of wait mode set-up settings and operation for entering wait mode are described here. (1) enables the interrupt used for returning from wait mode. (2) sets the interrupt enable flag (i flag) to 1. (3) clears the protection and changes the content of the system clock control register. (4) executes the wait instruction. operation wait mode (3) canceling protect b7 b0 protect register [address 000a 16 ] prcr 1 enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) 1 : write-enabled (4) wait instruction (3) control of cpu clock note: when switching the system clock, it is necessary to wait for the oscillation to stabilize. b7 b0 wait peripheral function clock stop bit 0 : do not stop f 1 , f 8 , f 32 in wait mode 1 : stop f 1 , f 8 , f 32 in wait mode port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit 0 : on 1 : off main clock division select bit 0 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note) 0 : x in , x out 1 : x cin , x cout system clock control register 0 [address 0006 16 ] cm0 b7 b0 system clock control register 1 [address 0007 16 ] cm1 0000 reserved bit must be set to ?? main clock division select bit 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 interrupt control register adic [address 004e 16 ] asioc [address 004f 16 ] fldic [address 0050 16 ] sitic(i=0, 1) [address 0051 16 , 0053 16 ] siric(i=0, 1) [address 0052 16 , 0054 16 ] taiic(i=0 to 4) [address 0055 16 to 0059 16 ] tbiic(i=0 to 2) [address 005a 16 to 005c 16 ] (1) setting interrupt to cancel wait mode make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (ipl) of the routine where the wait instruction is executed. interrupt priority level select bit b7 b0 intiic(i=0 to 2) [address 005d 16 to 005f 16 ] intiic(i=3 to 5) [address 0047 16 to 0049 16 ] make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (ipl) of the routine where the wait instruction is executed. interrupt priority level select bit b7 b0 0 reserved bit must be set to ?? (2) interrupt enable flag (i flag) ?
379 power control m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ____________ (1) when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. (2) when switching to either wait mode or stop mode, instructions occupying four bytes either from the wait instruction or from the instruction that sets the every-clock stop bit to 1 within the instruction queue are prefetched and then the program stops. so put at least four nops in succession either to the wait instruction or to the instruction that sets the every-clock stop bit to 1. (3) before the count source for bclk can be changed from x in to x cin or vice versa, the clock to which the count source is going to be switched must be oscillating stably. allow a wait time in software for the oscillation to stabilize before switching over the clock. (4) suggestions to reduce power consumption ? ports the processor retains the state of each programmable i/o port even when it goes to wait mode or to stop mode. a current flows in active i/o ports. a pass current flows in input ports that float. when entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (a) a-d converter a current always flows in the v ref pin. when entering wait mode or stop mode, set the vref connection bit to 0 so that no current flows into the v ref pin. (b) d-a converter the processor retains the d-a state even when entering wait mode or stop mode. disable the output from the d-a converter then work on the programmable i/o ports. (c) stopping peripheral functions in wait mode, stop non-used wait peripheral functions using the peripheral function clock stop bit. (d) switching the oscillation-driving capacity set the driving capacity to low when oscillation is stable. (e) external clock when using an external clock input for the cpu clock, set the main clock stop bit to 1. setting the main clock stop bit to 1 causes the x out pin not to operate and the power consumption goes down (when using an external clock input, the clock signal is input regardless of the content of the main clock stop bit). 2.14.4 precautions in power control
380 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 2.15 programmable i/o ports 2.15.1 overview forty-eight programmable i/o ports and forty high-breakdown-voltage output ports are available. i/o pins also serve as i/o pins for built-in peripheral functions. each port has a direction register that defines the i/o direction and also has a port register for i/o data. in addition, each port has a pull-up control register that defines pull-up in terms of 4 bits. ports p2, p3, and p4 0 Cp4 3 are high-breakdown-voltage p-channel open-drain output structure. these ports have no pull- up resistance. the following is an overview of the programmable i/o ports: (1) writing to a port register with the direction register set to output, the level of the written values from each relevant pin is output by writing to a port register. the output level conforms to cmos output or p-channel open-drain output. l level of port which is built-in pull-down resistor is apply voltage to the v ee pin. writing to the port register, with the direction register set to input, inputs a value to the port register, but nothing is output to the relevant pins. the output level remains floating. (2) reading a port register with the direction register set to output, reading a port register takes out the content of the port regis- ter, not the content of the pin. when the fld controller is used, reading the port register takes out fld output. with the direction register set to input, reading the port register takes out the content of the pin. (3) exclusive high-breakdown-voltage output port there are 40 exclusive output ports: p0 to p2, p5 and p6. all ports have structure of high-breakdown-voltage p-channel open drain output. exclusive output ports except p2 have built-in pull-down resistance. (4) setting pull-up the pull-up control bit allows setting of the pull-up, in terms of 4 bits, either in use or not in use. for the four bits chosen, pull-up is effective only in the ports whose direction register is set to input. pull-up is not effective in ports whose direction register is set to output. do not set pull-up of corresponding pin when x cin /x cout is set or a port is used as a-d input.
381 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (5) i/o functions of built-in peripheral devices table 2.15.1 shows relation between ports and i/o functions of built-in peripheral devices. table 2.15.1. relation between ports and i/o functions of built-in peripheral devices (6) examples of working on non-used pins table 2.15.2 contains examples of working on non-used pins. there are shown here for mere ex- amples. in practical use, make suitable changes and perform sufficient evaluation in compliance with you application. (a) single-chip mode table 2.15.2. examples of working on unused pins in single-chip mode port p0 to p3 internal peripheral device i/o pins fld controller output pins fld controller output pins p4 0 to p4 3 p5, p6 p7 0 to p7 2 timer b0 to b2 input pins p7 3 timer a0 i/o pin p7 4 to p7 7 timer a1 to a4 input pins/uart1 i/o pins p8 0 to p8 5 external interrupt input pins p8 6 , p8 7 sub-clock input pins p9 0 to p9 5 p9 6 a-d converter input pins p9 7 d-a converter output pin/ x in division clock output pin / dim signal output pin of fld controller fld controller output pins/uart0 i/o pins p4 4 to p4 7 p10 0 to p10 7 d-a converter output pin/clock i/o pin of serial i/o with automatic transfer function fld controller output pins i/o pins of serial i/o with automatic transfer function pin name connection ports p3, p4, p7 to p10 x out (note 2), v ee after setting for input mode, connect every pin to v ss or v cc via a resistor; or after setting for output mode, leave these pins open. (note 1) open av ss , v ref connect to v ss if setting these pins in output mode and opening them, ports are in input mode until switched into output mode by use of software after reset. thus the voltage levels of the pins become unstable, and there can be instances in which the power source current increases while the ports are in input mode. in view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes, setting the contents of the direction registers periodically by use of software increases program reliability. when an external clock is input to the x in pin. note 1: note 2: ports p0 to p2, p5, p6 open
382 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (7) registers related to the programmable i/o ports figure 2.15.1 shows the memory map of programmable i/o ports-related registers, and figures 2.15.2 to 2.15.4 show programmable i/o ports-related registers. figure 2.15.1. memory map of programmable i/o ports-related registers 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03fc 16 03fd 16 03fe 16 03ff 16 port p0 (p0) port p1 (p1) port p2 (p2) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) port p5 (p5) port p6 (p6) port p7 (p7) port p7 direction register (pd7) port p8 (p8) port p8 direction register (pd8) port p9 (p9) port p9 direction register (pd9) port p10 (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) 0359 16 035a 16 035b 16 035c 16 035d 16 p3 fld/port switch register (p3fpr) p5 digit output set register (p5dor) p6 digit output set register (p6dor) p4 fld/port switch register (p4fpr) p2 fld/port switch register (p2fpr)
383 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.15.2. programmable i/o ports-related registers (1) figure 2.15.3. programmable i/o ports-related registers (2) p o r t p i d i r e c t i o n r e g i s t e r s y m b o la d d r e s s w h e n r e s e t p d i ( i = 3 t o 1 0 , e x c e p t 5 , 6 )0 3 e 7 1 6 , 0 3 e a 1 6 , 0 3 e f 1 6 00 1 6 0 3 f 2 1 6 , 0 3 f 3 1 6 , 0 3 f 6 1 6 00 1 6 b i t n a m ef u n c t i o n b i t s y m b o lw r b 7b 6b 5b 4b 3b 2b 1b 0 p d i _ 0p o r t p i 0 d i r e c t i o n r e g i s t e r p d i _ 1p o r t p i 1 d i r e c t i o n r e g i s t e r p d i _ 2p o r t p i 2 d i r e c t i o n r e g i s t e r p d i _ 3p o r t p i 3 d i r e c t i o n r e g i s t e r p d i _ 4p o r t p i 4 d i r e c t i o n r e g i s t e r p d i _ 5p o r t p i 5 d i r e c t i o n r e g i s t e r p d i _ 6p o r t p i 6 d i r e c t i o n r e g i s t e r p d i _ 7p o r t p i 7 d i r e c t i o n r e g i s t e r 0 : i n p u t m o d e ( f u n c t i o n s a s a n i n p u t p o r t ) 1 : o u t p u t m o d e ( f u n c t i o n s a s a n o u t p u t p o r t ) ( i = 3 t o 1 0 e x c e p t 5 , 6 ) port pi register symbol addres when reset pi (i = 0 to 10) 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 indeterminate 03e9 16 , 03ec 16 , 03ed 16 , 03f0 16 , 03f1 16 , 03f4 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data (i = 0 to 10)
384 programmable i/o ports m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 2.15.4. programmable i/o ports-related registers (3) p u l l - u p c o n t r o l r e g i s t e r 0 s y m b o l a d d r e s s w h e n r e s e t p u r 0 0 3 fd 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 p u 0 1p 4 4 t o p 4 7 p u l l - u p p u 0 6p 7 0 t o p 7 3 p u l l - u p p u 0 7p 7 4 t o p 7 7 p u l l - u p p u l l - u p c o n t r o l r e g i s t e r 1 s y m b o l a d d r e s s w h e n r e s e t p u r 1 0 3 f e 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 p u 1 0p 8 0 t o p 8 3 p u l l - u p p u 1 1p 8 4 t o p 8 7 p u l l - u p p u 1 2p 9 0 t o p 9 3 p u l l - u p p u 1 3p 9 4 t o p 9 7 p u l l - u p p u 1 4p 1 0 0 t o p 1 0 3 p u l l - u p p u 1 5p 1 0 4 t o p 1 0 7 p u l l - u p t h e c o r r e s p o n d i n g p o r t i s p u l l e d h i g h w i t h a p u l l - u p r e s i s t o r 0 : n o t p u l l e d h i g h 1 : p u l l e d h i g h t h e c o r r e s p o n d i n g p o r t i s p u l l e d h i g h w i t h a p u l l - u p r e s i s t o r 0 : n o t p u l l e d h i g h 1 : p u l l e d h i g h n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . t h e c o r r e s p o n d i n g p o r t i s p u l l e d h i g h w i t h a p u l l - u p r e s i s t o r 0 : n o t p u l l e d h i g h 1 : p u l l e d h i g h n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e .
chapter 3 examples of peripheral functions applications
386 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r this chapter presents applications in which peripheral functions built in the M30218 are used. they are shown here as examples. in practical use, make suitable changes and perform sufficient evaluation. for basic use, see chapter 2 peripheral functions usage. here follows the list of applications that appear in this chapter. ? 3.1 long-period timers ....................................................................................................... ....... p388 ? 3.2 variable-period variable-duty pwm output ......................................................................... p392 ? 3.3 delayed one-shot output .................................................................................................. .. p396 ? 3.4 buzzer output ............................................................................................................ ......... p400 ? 3.5 solution for external interrupt pins shortage ....................................................................... p402 ? 3.6 memory to memory dma transfer ...................................................................................... p404 ? 3.7 controlling power using stop mode .................................................................................... p408 ? 3.8 controlling power using wait mode ..................................................................................... p41 2 applications
387 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r applications this page kept blank for layout purposes.
388 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 3.1 long-period timers overview specifications operation figure 3.1.1. operation timing of long-period timers in this process, timer a0 and timer a1 are connected to make a 16-bit timer with a 16-bit prescaler. figure 3.1.1 shows the operation timing, figure 3.1.2 shows the connection dia- gram, and figures 3.1.3 and 3.1.4 show the set-up procedure. use the following peripheral functions: ? timer mode of timer a ? event counter mode of timer a (1) set timer a0 to timer mode, and set timer a1 to event counter mode. (2) perform a count on count source f 1 using timer a0 to count for 1 ms, and perform a count on timer a0 using timer a1 to count for 1 second. (3) connect a 10-mhz oscillator to x in . (1) setting the count start flag to 1 causes the counter to begin counting. the counter of timer a0 performs a down count on count source f 1 . (2) if the counter of timer a0 underflows, the counter reloads the content of the reload register and continues counting. at this time, the timer a0 interrupt request bit goes to 1. the counter of timer a1 performs a down count on underflows in timer a0. (3) if the counter of timer a1 underflows, the counter reloads the content of the reload register and continues counting. at this time, the timer a1 interrupt request bit goes to 1. ffff 16 l 0000 16 timer a0 counter content (hex) l = reload register content timer a1 count start flag ? ? timer a1 interrupt request bit ? ? timer a0 interrupt request bit ? ? timer a0 count start flag ? ? timer a1 counter content (hex) 0000 16 n ffff 16 time (1) start count start count. time n = reload register content set to ?? by software set to ?? by software cleard ?? by software cleared to ??when interrupt request is accepted, or cleared by software (2) timer a0 underflow (3) timer a1 underflow
389 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.1.2. connection diagram of long-period timers f 1 f 8 f 32 f c32 timer a0 timer a1 timer a0 interrupt request bit timer a1 interrupt request bit used for timer mode used for event counter mode
390 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.1.3. set-up procedure of long-period timers (1) continued to the next page setting timer a0 selecting timer mode and functions pulse output function select bit 0 : pulse is not output (ta0 out pin is a normal port pin) timer a0 mode register [address 0396 16 ] ta0mr gate function select bit 0 0 : gate function not available (ta0 in pin is a normal port pin) b4 b3 selection of timer mode b7 b0 00 00 0 0 (must always be ??in timer mode) count source select bit 0 0 : f 1 b7 b6 0 00 setting divide ratio b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 27 16 0f 16 selecting event counter mode and each function setting timer a1 pulse output function select bit 0 : pulse is not output (ta1 out pin is a normal port pin) timer a1 mode register [address 0397 16 ] ta1mr up/down switching cause select bit 0 : up/down flag content selection of event counter mode fix to ??when counting timer overflow flag count operation type select bit 0 : reload type 0 (must always be ??in event counter mode) count polarity select bit b7 b0 01 00 00 0 0 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32
391 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.1.4. set-up procedure of long-period timers (2) start counting continued from the previous page b7 b0 trigger select register [address 0383 16 ] trgsr timer a1 event/trigger select bit 1 0 : ta0 overflow is selected b1 b0 0 1 setting trigger select register setting divide ratio b7 b0 (b15) (b8) b7 b0 timer a1 register [address 0389 16 , 0388 16 ] ta1 03 16 e7 16 setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag 1 : starts counting timer a1 count start flag 1 : starts counting b7 b0 1 1
392 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r in this process, timer a0 and a1 are used to generate variable-period, variable-duty pwm out- put. figure 3.2.1 shows the operation timing, figure 3.2.2 shows the connection diagram, and figures 3.2.3 and 3.2.4 show the set-up procedure. use the following peripheral functions: ? timer mode of timer a ? one-shot timer mode of timer a (1) set timer a0 in timer mode, and set timer a1 in one-shot timer mode with pulse-output function. (2) set 1 ms, the pwm period, to timer a0. set 500 m s, the width of pwm h pulse, to timer a1. both timer a0 and timer a1 use f 1 for the count source. (3) connect a 10-mhz oscillator to x in . (1) setting the count start flag to 1 causes the counter of timer a0 to begin counting. the counter of timer a0 performs a down count on count source f 1 . (2) if the counter of timer a0 underflows, the counter reloads the content of the reload register and continues counting. at this time, the timer a0 interrupt request bit gose to 1. (3) an underflow in timer a0 triggers the counter of timer a1 and causes it to begin counting. when the counter of timer a1 begins counting, the output level of the ta1 out pin gose to h. (4) as soon as the count of the counter of timer a1 becomes 0000 16 , the output level of ta1 out pin gose to l, and the counter reloads the content of the reload register and stops counting. at the same time, the timer a1 interrupt request bit gose to 1. 3.2 variable-period variable-duty pwm output overview specifications operation
393 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.2.2. connection diagram of variable-period variable-duty pwm output figure 3.2.1. operation timing of variable-period variable-duty pwm output ffff 16 l 0000 16 timer a0 counter content (hex) l = reload register content ? ? ? ? ? ? ? ? timer a1 counter content (hex) 0001 16 n ffff 16 time (1) timer a0 start count time timer a1 count start flag timer a1 interrupt request bit timer a0 interrupt request bit timer a0 count start flag pwm pulse output from ta1 out pin ? ? n = reload register content aaa aaa set to 1 by software set to 1 by software cleared to 0 when interrupt request is accepted, or cleared by software cleared to 0 when interrupt request is accepted, or cleared by software 1ms 500s (2) timer a0 underflow (3) timer a1 start count (4) timer a1 stop count f 1 f 8 f 32 f c32 timer a0 timer a1 timer a0 interrupt request bit timer a1 interrupt request bit used for timer mode (set to period) used for one-shot timer mode (set to h width)
394 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.2.3. set-up procedure of variable-period variable-duty pwm output (1) continued to the next page setting timer a0 pulse output function select bit 0 : pulse is not output (ta0 out pin is a normal port pin) selecting timer mode and functions timer a0 mode register [address 0396 16 ] ta0mr gate function select bit 0 0 : gate function not available (ta0 in pin is a normal port pin) b4 b3 selection of timer mode b7 b0 00 00 0 0 (must always be ??in timer mode) count source select bit 0 0 : f 1 b7 b6 00 0 setting divide ratio b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 27 16 0f 16 setting timer a1 pulse output function select bit 1 : pulse is output selecting one-shot timer mode and functions timer a1 mode register [address 0397 16 ] ta1mr external trigger select bit (invalid when choosing timer's overflow as trigger) selection of one-shot timer mode b7 b0 10 01 1 0 (must always be ??in one-shot timer mode) trigger select bit 1 : selected by event/trigger select register 0 0 0 count source select bit 0 0 : f 1 b7 b6 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32
395 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.2.4. set-up procedure of variable-period variable-duty pwm output (2) start counting continued from the previous page b7 b0 trigger select register [address 0383 16 ] trgsr timer a1 event/trigger select bit 1 0 : ta0 overflow is selected b1 b0 0 1 setting trigger select register setting one-shot timer's time b7 b0 (b15) (b8) b7 b0 timer a1 register [address 0389 16 , 0388 16 ] ta1 13 16 88 16 setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag 1 : starts counting timer a1 count start flag 1 : starts counting b7 b0 1 1
396 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r the following are steps of outputting a pulse only once after a specified elapse since an external trigger is input. figure 3.3.1 shows the operation timing, figure 3.3.2 shows the connection dia- gram, and figures 3.3.3 and 3.3.4 show the set-up procedure. use the following peripheral function: ? one-shot timer mode of timer a (1) set timer a0 in one-shot timer mode, and set timer a1 in one-shot timer mode with pulse- output function. (2) set 1 ms, an interval before a pulse is output, in timer a0; and set 50 m s, a pulse width, in timer a1. both timer a0 and timer a1 use f 1 for the count source. (3) connect a 10-mhz oscillator to x in . (1) setting the trigger select bit to 1 and setting the count start flag to 1 enables the counter of timer a0 to count. (2) if an effective edge, selected by use of the external trigger select bit, is input to the ta0 in pin, the counter begins a down count. the counter of timer a0 performs a down count on count source f 1 . (3) as soon as the counter of timer a0 becomes 0000 16 , the counter reloads the content of the reload register and stops counting. at this time, the timer a0 interrupt request bit gose to 1. (4) an underflow in timer a0 triggers the counter of timer a1 and causes it to begin counting. when timer a1 begins counting, the output level of the ta1 out pin gose to h. (5) as soon as the counter of timer a1 becomes 0000 16 , the output level of the ta1 out pin gose to l, the counter reloads the content of the reload register, and stops counting. at this time, timer a1 interrupt request bit gose to 1. 3.3 delayed one-shot output overview specifications operation
397 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.3.1. operation timing of delayed one-shot output figure 3.3.2. connection diagram of delayed one-shot output ffff 16 l 0001 16 timer a0 counter content (hex) l = reload register content ? ? ? ? ? ? ? ? timer a1 counter content (hex) 0001 16 n ffff 16 time (2) timer a0 start count time timer a1 count start flag timer a1 interrupt request bit timer a0 interrupt request bit timer a0 count start flag input signal from ta0 in pin pwm pulse output from ta1 out pin set to ?? by software set to ?? by software ? ? cleared to ??when interrupt request is accepted, or cleared by software cleared to ??when interrupt request is accepted, or cleared by software ? ? 1ms 50s (1) count enabled (3) timer a0 stop count (4) timer a1 start count (5) timer a1 stop count n = reload register content f 1 f 8 f 32 f c32 timer a0 timer a1 timer a0 interrupt request bit timer a1 interrupt request bit used for one-shot timer mode used for one-shot timer mode ta0 in pin input
398 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.3.3. set-up procedure of delayed one-shot output (1) continued to the next page setting timer a0 setting one-shot start flag (select ta0 in pin to input ta0 trigger) b7 b0 one-shot start flag [address 0382 16 ] onsf timer a0 event/trigger select bit 0 0 : input on ta0 in is selected (note) b7 b6 note: set the corresponding port direction register to ?? setting delay time b7 b0 (b15) (b8) b7 b0 timer a0 register [address 0387 16 , 0386 16 ] ta0 27 16 10 16 pulse output function select bit 0 : pulse is not output (ta0 out pin is normal port pin) selecting one-shot timer mode and functions timer a0 mode register [address 0396 16 ] ta0mr external trigger select bit 0 : falling edge of ta0 in pin's input signal selection of one-shot timer mode b7 b0 10 00 1 0 (must always be ??in one-shot timer mode) count source select bit 0 0 : f 1 b7 b6 trigger select bit 1 : selected by event/trigger select register 0 00 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32
399 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.3.4. set-up procedure of delayed one-shot output (2) start counting continued from the previous page setting one-shot timer's time b7 b0 (b15) (b8) b7 b0 timer a1 register [address 0389 16 , 0388 16 ] ta1 01 16 f4 16 setting count start flag count start flag [address 0380 16 ] tabsr timer a0 count start flag 1 : starts counting timer a1 count start flag 1 : starts counting b7 b0 11 setting timer a1 selecting one-shot timer mode and functions pulse output function select bit 1 : pulse is output (ta1 out pin is pulse output pin) timer a1 mode register [address 0397 16 ] ta1mr external trigger select bit invalid when choosing timer's overflow selection of one-shot timer mode b7 b0 10 01 1 0 (must always be ??in one-shot timer mode) count source select bit 0 0 : f 1 b7 b6 trigger select bit 1 : selected by event/trigger select register 0 00 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32 setting trigger select register (set timer a0 to trigger timer a1) b7 b0 trigger select register [address 0383 16 ] trgsr 0 1 timer a1 event/trigger select bit 1 0 : ta0 overflow is selected b1 b0
400 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 3.4 buzzer output overview specifications operation figure 3.4.1. operation timing of buzzer output the timer mode is used to make the buzzer ring. figure 3.4.1 shows the operation timing, and figure 3.4.2 shows the set-up procedure. use the following peripheral function: ? the pulse-outputting function in timer mode of timer a. (1) sound a 2-khz buzz beep by use of timer a0. (2) effect pull-up in the relevant port by use of a pull-up resistor. when the buzzer is off, set the port high-impedance, and stabilize the potential resulting from pulling up. (3) connect a 10-mhz oscillator to x in . (1) the microcomputer begins performing a count on timer a0. timer a0 has disabled interrupts. (2) the microcomputer begins pulse output by setting the pulse output function select bit to pulse output effected. p7 5 changes into ta0 out pin and outputs 2-khz pulses. (3) the microcomputer stops outputting pulses by setting the pulse output function select bit to pulse output not effected. p7 5 goes to an input pin, and the output from the pin becomes high-impedance. ? ? ? ? timer a0 overflow timing count start flag pulse output function select bit p7 5 output ? ? high-impedance high-impedance (1) start count (2) buzzer output on (3) buzzer output off
401 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.4.2. set-up procedure of buzzer output initialization of timer a0 b7 b0 selection of timer mode pulse output function select bit 0 : pulse is not output (ta0 out pin is a normal port pin) gate function select bit b4 b3 0 0 : gate function not available (ta0 in pin is a normal port pin) 0 (must always be ??in timer mode) count source select bit b7 b6 0 0 : f 1 timer a0 mode register ta0mr [address 0396 16 ] 00 00 0 00 0 timer a0 register ta0 [address 0387 16 , 0386 16 ] b15 b8 b7 b0 09 16 c4 16 b7 b0 count start flag [address 0380 16 ] tabsr b7 b0 timer a0 count start flag 1 : starts counting 1 initialization of port p7 direction register b7 b0 port p7 5 direction register 0 : input mode 0 port p7 direction register [address 03ef 16 ] pd7 b7 b0 pulse output function select bit 1 : pulse is output (port p7 5 is ta0 out output pin) timer a0 mode register [address 0396 16 ] ta0mr buzzer on 1 b7 b0 pulse output function select bit 0 : pulse is not output timer a0 mode register [address 0396 16 ] ta0mr buzzer off 0 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2 m s 976.56 m s 00 01 10 11 f 1 f 8 f 32 f c32
402 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 3.5 solution for external interrupt pins shortage overview specifications operation the following are solution for external interrupt pins shortage. figure 3.5.1 shows the set-up procedure. use the following peripheral function: ? event counter mode of timer a (1) inputting a falling edge to the ta0 in pin generates a timer a0 interrupt. (1) set timer a0 to event counter mode, set timer to 0, and set interrupt priority levels in timer a0. (2) inputting a falling edge to the ta0 in pin generates a timer a0 interrupt.
403 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.5.1. set-up procedure of solution for a shortage of external interrupt pins initialization of timer a0 b7 b0 selection of event counter mode pulse output function select bit 0 : pulse is not output (ta0 out pin is a normal port pin) count polarity select bit 0 : counts external signal's falling edge up/down switching cause select bit 0 : up/down flag's content 0 (must always be ??in event counter mode) count operation type select bit 0 : reload type 0 (must always be ??in event counter mode) timer a0 mode register ta0mr [address 0396 16 ] 00 00 1 00 0 up/down flag [address 0384 16 ] udf b7 b0 timer a0 up/down flag 0 : down count 0 setting interrupt priority levels in timer a0 b7 b0 timer a0 interrupt control register [address 0055 16 ] ta0ic interrupt control level (set a value 1 to 7) setting interrupt enable flag (i flag) b7 b0 timer a0 count start flag 1 : starts counting count start flag [address 0380 16 ] tabsr 1 initialization of port p7 direction register b7 b0 port p7 3 direction register 0 : input mode 0 port p7 direction register [address 03ef 16 ] pd7 timer a0 register ta0 [address 0387 16 , 0386 16 ] b15 b8 b7 b0 00 16 00 16 b7 b0
404 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 3.6 memory to memory dma transfer the following are steps for changing both source address and destination address to transfer data from memory to another. the dma transfer utilizes the workings that assign a higher priority to the dma0 transfer if transfer requests simultaneously occur in two dma channels. figure 3.6.1 shows the operation timing, figure 3.6.2 shows the block diagram, and figures 3.6.3 and 3.6.4 show the set-up procedure. use the following peripheral functions: ? timer mode of timer a ? two dmac channels ? one-byte temporary ram (address 0800 16 ) (1) transfer the content of memory extending over 128 bytes from address f8000 16 to a 128- byte area starting from address 00400 16 . transfer the content every time a timer a0 interrupt request occurs. (2) use dma0 for a transfer from the source to built-in memory, and dma1 for a transfer from built-in memory to the destination. (1) a timer a interrupt request occurs. though both a dma0 transfer request and a dma1 trans- fer request occur simultaneously, the former is executed first. (2) dma0 receives a transfer request and transfers data from the source to the built-in memory. at this time, the source address is incremented. (3) next, dma1 receives a transfer request and transfers data involved from built-in memory to the destination. at this time, the destination address is incremented. overview specifications operation figure 3.6.1. operation timing of memory to memory dma transfer dmac applications timer a0 transfer request address bus ? ? ? ? ? ? (1) transfer request generation (2) start dma0 transferring (3) start dma1 transferring instruction cycle dma0 operation dma1 operation f8000 16 0800 16 0800 16 00400 16 wr signal rd signal source address destination address source address destination address the dma0 operation and dma1 operation are not necessarily executed in succession due to the a cycle steal operation. the instruction cycle varies from instruction to instruction. since the parts of the rd and wr signals shown in short-dash lines vary in step with writing to the internal ram, waveforms are not output to the rd and wr pins. note 1: note 2: note 3:
405 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.6.2. block diagram of memory to memory dma transfer dmac applications 00400 16 0047f 16 source area data transfer by dma0 f8000 16 f807f 16 destination area data transfer by dma1 800 16 temporary ram f8000 16 content f8001 16 content f8002 16 content f807f 16 content
406 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.6.3. set-up procedure of memory to memory dma transfer (1) dmac applications continued to the next page initialization of dma0 b7 b0 dma request cause select bit b3 b2 b1 b0 0 0 1 0 : timer a0 dma0 request cause select register dm0sl [address 03b8 16 ] 01 00 0 software dma request bit 0 : software is not generated b15 b8 b7 b0 80 16 00 16 dma0 source pointer sar0 [address 0022 16 , 0021 16 , 0020 16 ] b7 b0 b23 b16 0f 16 b7 b0 b15 b8 b7 b0 08 16 00 16 dma0 destination dar0 [address 0026 16 , 0025 16 , 0024 16 ] pointer b7 b0 b23 b16 00 16 b7 b0 b15 b8 b7 b0 00 16 7f 16 dma0 transfer counter tcr0 [address 0029 16 , 0028 16 ] b7 b0 transfer unit bit select bit 1 : 8 bits repeat transfer mode select bit 1 : repeat transfer dma request bit 0 : dma not requested dma enable bit 1 : enabled source address direction select bit 1 : forward destination address direction select bit 0 : fixed b7 b0 dma0 control register dm0con [address 002c 16 ] 1 10 1 01 b15 b8 b7 b0 08 16 00 16 dma1 source pointer sar1 [address 0032 16 , 0031 16 , 0030 16 ] b7 b0 b23 b16 00 16 b7 b0 b15 b8 b7 b0 04 16 00 16 b7 b0 b23 b16 00 16 b7 b0 b15 b8 b7 b0 00 16 7f 16 dma1 transfer counter tcr1 [address 0039 16 , 0038 16 ] b7 b0 initialization of dma1 b7 b0 dma request cause select bit b3 b2 b1 b0 0 0 1 0 : timer a0 dma0 request cause select register dm1sl [address 03ba 16 ] 01 00 0 software dma request bit 0 : software is not generated transfer unit bit select bit 1 : 8 bits repeat transfer mode select bit 1 : repeat transfer dma request bit 0 : dma not requested dma enable bit 1 : enabled source address direction select bit 0 : fixed destination address direction select bit 1 : forward b7 b0 dma1 control register dm1con [address 003c 16 ] 1 10 1 10 dma1 destination pointer dar1 [address 0036 16 , 0035 16 , 0034 16 ]
407 timer a applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.6.4. set-up procedure of memory to memory dma transfer (2) dmac applications timer a0 count start flag 1 : starts counting continued from the previous page initialization of timer a0 timer a0 mode register ta0mr [address 0396 16 ] timer a0 register ta0 [address 0387, 0386 16 ] b15 b8 b7 b0 27 16 0f 16 b7 b0 b7 b0 1 selection of timer mode pulse output function select bit 0 : pulse is not output (ta0 out pin is a normal port pin) gate function select bit b4 b3 0 0 : gate function not available (ta0 in pin is a normal port pin) 0 (must always be fixed to ??in timer mode) count source select bit b7 b6 0 0 : f 1 count source period f(x in ) : 10mh z f(xc in ) : 32.768kh z b7 b6 count source 100ns 800ns 3.2s 976.56s 00 01 10 11 f 1 f 8 f 32 f c32 b7 b0 00 00 0 00 0 count start flag [address 0380 16 ] tabsr
408 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r overview specifications operation 3.7 controlling power using stop mode the following are steps for controlling power using stop mode. figure 3.7.1 shows the operation timing, figure 3.7.2 shows an example of circuit, and figures 3.7.3 and 3.7.4 show the set-up procedure. use the following peripheral functions: ________ ? int5 interrupt ? stop mode (1) use int5 for the int interrupt. use the p8 5 /int5 pin as an input pin. ________ (2) when a int5 interrupt request occurs, the stop mode is cleared. ________ (1) enable int5 interrupt and set the pull-up function to the p8 5 pin. ________ (2) stop x in to enter the stop mode. enable int5 interrupt at this time. ________ (3) when a int5 interrupt request occurs by falling edge input to the p8 5 pin, the stop mode is cleared. execute the return processing for the other interrupts, which are stopped, in the ________ int5 interrupt processing and others. figure 3.7.1. operation timing of controlling power using stop mode (1) enter stop mode (2) clear stop mode (3) return processing int5 input int5 interrupt processing cpu clock stop mode
409 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.7.2. example of circuit of controling power using stop mode p8 5 / int5 v ref i/o port key input
410 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.7.3. set-up procedure of controlling power using stop mode (1) canceling protect protect register [address 000a 16 ] prcr b7 b0 1 enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) 1 : write-enabled main nop instruction x 5 int5 interrupt request generation initial condition b7 b0 pull-up control register 2 [address 03fe 16 ] pur2 p8 4 to p8 7 pulled high 1 port p8 direction register [address 03f2 16 ] pd8 b7 b0 0 set p8 5 to input port interrupt enable level (ipl) = 0 interrupt enable flag (i) = 1 int5 interrupt control register [address 0049 16 ] int5ic interrupt priority level select bit set higher value than the present ipl b7 b0 1 0 0 setting interrupt except stop mode cancel i nterrupt control register dmiic(i=0, 1) [address 004b 16 , 004c 16 ] adic [address 004e 16 ] asioic [address 004f 16 ] fldic [address 0050 16 ] sitic(i=0, 1) [address 0051 16 , 0053 16 ] siric(i=0, 1) [address 0052 16 , 0054 16 ] taiic(i=0 to 4) [address 0055 16 to 0059 16 ] tbiic(i=0 to 2) [address 005a 16 to 005c 16 ] interrupt priority level select bit 000 : interrupt disabled b7 b0 0 0 0 interrupt priority level select bit 000 : interrupt disabled b7 b0 0 0 0 intiic(i=0 to 4) [address 0047 16 to 0048 16 ] [address 005d 16 to 005f 16 ] 0 reserved bit always set to ? all clocks off (stop mode) system clock control register 1 [address 0007 16 ] cm1 b7 b0 all clock stop control bit 1 : all clocks off (stop mode) 1 0000 reserved bit always set to ? setting operation clock after returning from stop mode system clock control register 0 [address 0006 16 ] cm0 x cin -x cout generation port x c select bit b7 b0 system clock select bit x cin , x cout as this register becomes setting mentioned above when operating with x cin (count source of bclk is x cin ), the user does not need to set it again. when operating with x in , set port xc select bit to ??before setting system clock select bit to ?? the both bits cannot be set at the same time. 1 1 (when operating with x cin after returning) system clock control register 0 [address 0006 16 ] cm0 on main clock (x in -x out ) stop bit b7 b0 system clock select bit x in , x out as this register becomes setting mentioned above when operating with x in (count source of bclk is x in ), the user does not need to set it again. 00 (when operating with x in after returning) polarity select bit 0 : selects falling edge reserved bit always set to ? 0 0
411 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.7.4. set-up procedure of controlling power using stop mode (2) int5 interrupt store the registers reit instruction restore the registers i nterrupt control register dmiic(i=0, 1) [address 004b 16 , 004c 16 ] adic [address 004e 16 ] asioic [address 004f 16 ] fldic [address 0050 16 ] sitic(i=0, 1) [address 0051 16 , 0053 16 ] siric(i=0, 1) [address 0052 16 , 0054 16 ] taiic(i=0 to 4) [address 0055 16 to 0059 16 ] tbiic(i=0 to 2) [address 005a 16 to 005c 16 ] interrupt priority level select bit set interrupt priority level of used interrupt to these bits again b7 b0 interrupt priority level select bit set interrupt priority level of used interrupt to these bits again b7 b0 0 0 0 intiic(i=0 to 4) [address 0047 16 to 0048 16 ] [address 005d 16 to 005f 16 ] 0 always set to ? returning interrupt except stop mode cancel
412 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 3.8 controling power using wait mode the following are steps for controling power using wait mode. figure 3.8.1 shows the operation timing, and figures 3.8.2 to 3.8.4 show the set-up procedure. use the following peripheral functions: ? timer mode of timer b ? wait mode a flag named f-wit is used in the set-up procedure. the purpose of this flag is to decide whether or not to clear wait mode. if f_wit = 1 in the main program, the wait mode is entered; if f_wit = 0, the wait mode is cleared. (1) connect a 32.768-khz oscillator to x cin to serve as the timer count source. as interrupts occur every one second, which is a count the timer reaches, the controller returns from wait mode and count the clock using a program. ________ (2) clear wait mode if a int0 interrupt request occurs. (1) switch the system clock from x in to x cin to get low-speed mode. _______ (2) stop x in and enter wait mode. in this instance, enable the timer b2 interrupt and the int0 interrupt. (3) when a timer b2 interrupt request occurs (at 1-second intervals), start supplying the bclk from x cin. at this time, count the clock within the routine that handles the timer b2 interrupts and enter wait mode again. _______ (4) if a int0 interrupt occurs, start supplying the bclk from x cin . start the x in oscillation within _______ the int0 interrupt, and switch the bclk count source to x in after oscillation is stabilized. overview specifications operation figure 3.8.1. operation timing of controling power using wait mode timer b2 interrupt processing timer b overflow x cin x out bclk int 0 (1) shift to low-speed mode (2) stop x in (3) timer b2 interrupt (4) int 0 interrupt ? ? high-speed low-speed low-speed low-speed low-speed high-speed
413 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.8.2. set-up procedure of controlling power using wait mode (1) main setting interrupt except clearing wait mode interrupt control register dmiic (i = 0, 1) [address 004b 16 , 004c 16 ] adic [address 004e 16 ] asioic [address 004f 16 ] fldic [address 0050 16 ] sitic (i = 0, 1) [address 0051 16 , 0053 16 ] siric (i = 0, 1) [address 0052 16 , 0054 16 ] taiic (i = 0 to 4) [address 0055 16 to 0059 16 ] tbiic (i = 0 to 2) [address 005a 16 to 005c 16 ] intiic (i =1 to 5) [address 0047 16 to 0049 16 ] [address 005e 16 , 005f 16 ] b7 b0 0 0 0 interrupt priority level select bit b2 b1 b0 0 0 0 : interrupt disabled initial condition interrupt priority level (ipl) = 0 interrupt enable flag (i) = 1 b15 b8 b7 b0 03 16 ff 16 timer b2 register [address 0395 16 , 0394 16 ] tb2 b7 b0 1 clock prescaler reset flag [address 0381 16 ] cpsrf rrescaler is reset b7 b0 count start flag [address 0380 16 ] tabsr 1 tb2 start counting b7 b0 1 0 0 timer b2 interrupt control register [address 005c 16 ] tb2ic tb2 interrupt priority level system clock select bit 0 : x in -x out b7 b0 wait state internal clock stop bit 001 system clock control register 0 [address 0006 16 ] cm0 port xc select bit 1 : functions as x cin -x cout oscillator main clock (x in -x out ) stop bit 0 : oscillating main clock divide ratio select bit 0 x cin -x cout drive capacity select bit b7 b0 timer b2 mode register [address 039d 16 ] tb2mr 10 0 1 operation mode select bit b1 b0 0 0 : timer mode count source select bit b7 b6 1 1 : f c32 (f(x cin ) divided by 32) b7 b0 1 0 0 int0 interrupt control register [address 005d 16 ] int0ic int0 interrupt priority level continued to the next page 0
414 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.8.3. set-up procedure of controlling power using wait mode (2) canceling protect protect register [address 000a 16 ] prcr b7 b0 1 enables writing to system clock control registers 0 and 1 (address 0006 16 and 0007 16 ) 1 : write-enabled switching system clock b7 b0 system clock select bit 1 : x cin -x cout 1 system clock control register 0 [address 0006 16 ] cm0 b7 b0 main clock (x in -x out ) stop bit 1 : off 1 system clock control register 0 [address 0006 16 ] cm0 stopping main clock [f_wit] = 1 wait instruction switching system clock b7 b0 system clock select bit 0 : x in -x out 0 system clock control register 0 [address 0006 16 ] cm0 b7 b0 main clock (x in -x out ) stop bit 0 : on 0 system clock control register 0 [address 0006 16 ] cm0 starting main clock oscillator [f_wit] : 1 = 1 tb2 interrupt request generated int0 interrupt request generated nop instruction x 5 continued from the previous page wait until the main clock has stabilized
415 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 3.8.4. set-up procedure of controlling power using wait mode (3) store the registers restore the registers reit instruction [f_wit] = 0 int0 interrupt store the registers restore the registers reit instruction counting clock timer b2 interrupt
416 controlling power applications m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r this page kept blank for layout purposes.
chapter 4 interrupt
418 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 4.1.1. classification of interrupts interrupt ? ? ? y ? ? ? t software hardware ? y ? t special peripheral i/o (note) ? y ? t undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? y ? ? t reset ________ dbc watchdog timer single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. 4.1 overview of interrupt 4.1.1 type of interrupts figure 4.1.1 lists the types of interrupts.
419 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 4.1.2 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to 1. the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o interrupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to 0 and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt re- quest. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
420 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 4.1.3 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset ____________ reset occurs if an l is input to the reset pin. ________ ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt generated by the watchdog timer. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to 1, a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. for address match interrupt, see 2.13 address match interrupt. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? dma0 interrupt, dma1 interrupt these are interrupts dma generates. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0 and uart1 transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0 and uart1 reception interrupt these are interrupts that the serial i/o reception generates. ? si/o automatic transfer interrupt this is an interrupt that the si/o automatic transfer generates. ? fld interrupt this is an interrupt that fld generates. ? timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates. ? timer b0 interrupt through timer b2 interrupt these are interrupts that timer b generates. ________ ________ ? int0 interrupt through int5 interrupt ______ ______ an int interrupt occurs if either a rising edge or a falling edge is input to the int pin.
421 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector contains ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use - ffff8 16 to ffffb 16 - reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only. 4.1.4 interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 4.1.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. table 4.1.1. interrupts assigned to the fixed vector tables and addresses of vector tables
422 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r table 4.1.2. interrupts assigned to the variable vector tables and addresses of vector tables ?variable vector tables the addresses in the variable vector table can be modified, according to the users settings. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the ad- dress the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 4.1.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked i flag +0 to +3 (note) brk instruction software interrupt number 0 +44 to +47 (note) software interrupt number 11 +48 to +51 (note) software interrupt number 12 +56 to +59 (note) software interrupt number 14 +68 to +71 (note) software interrupt number 17 +72 to +75 (note) software interrupt number 18 +76 to +79 (note) software interrupt number 19 +80 to +83 (note) software interrupt number 20 +84 to +87 (note) software interrupt number 21 +88 to +91 (note) software interrupt number 22 +92 to +95 (note) software interrupt number 23 +96 to +99 (note) software interrupt number 24 +100 to +103 (note) software interrupt number 25 +104 to +107 (note) software interrupt number 26 +108 to +111 (note) software interrupt number 27 +112 to +115 (note) software interrupt number 28 +116 to +119 (note) software interrupt number 29 +120 to +123 (note) software interrupt number 30 +124 to +127 (note) software interrupt number 31 +128 to +131 (note) software interrupt number 32 +252 to +255 (note) software interrupt number 63 to note : address relative to address in interrupt table register (intb). cannot be masked i flag to a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3 timer b0 timer b1 int0 int1 software interrupt +28 to +31 (note) int3 software interrupt number 7 +32 to +35 (note) int4 software interrupt number 8 +36 to +39 (note) int5 software interrupt number 9 dma0 dma1 +60 to +63 (note) software interrupt number 15 si/o automatic transfer +64 to +67 (note) software interrupt number 16 fld timer a4 timer b2 int2
423 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 4.2.1. memory map of the interrupt control registers 4.2 interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a non-maskable interrupt using the interrupt enable flag (i flag), interrupt priority level selection bit, or processor interrupt priority level (ipl). whether an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 4.2.1 shows the memory map of the interrupt control registers, and figure 4.2.2 shows the interrupt control registers. 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 int1 interrupt control register (int1ic) timer b0 interrupt control register (tb0ic) timer b2 interrupt control register (tb2ic) timer a1 interrupt control register (ta1ic) timer a3 interrupt control register (ta3ic) uart0 transmit interrupt control register (s0tic) int2 interrupt control register (int2ic) int0 interrupt control register (int0ic) timer b1 interrupt control register (tb1ic) timer a0 interrupt control register (ta0ic) timer a2 interrupt control register (ta2ic) timer a4 interrupt control register (ta4ic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control regster(s1tic) uart1 receive interrupt control register(s1ric) dma1 interrupt control register (dm1ic) dma0 interrupt control register (dm0ic) a-d conversion interrupt control register (adic) si/o2 transmit interrupt control register (asioic) fld interrupt control register (fldic) int4 interrupt control register (int4ic) int5 interrupt control register (int5ic) int3 interrupt control register (int3ic)
424 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 4.2.2. interrupt control registers symbol address when reset intiic(i=0 to 5) 005d 16 to 005f 16 xx00x000 2 0047 16 to 0049 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 note1 : this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. (note1) interrupt control register(note2) b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa bit name function bit symbol w r symbol address when reset dmiic(i=0, 1) 004b 16 to 004c 16 xxxxx000 2 adic 004e 16 xxxxx000 2 asioic 004f 16 xxxxx000 2 fldic 0050 16 xxxxx000 2 sitic(i=0, 1) 0051 16 , 0053 16 xxxxx000 2 siric(i=0, 1) 0052 16 , 0054 16 xxxxx000 2 taiic(i=0 to 4) 0055 16 to 0059 16 xxxxx000 2 tbiic(i=0 to 2) 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. (note1) note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 a a a a a a a a a a a a a a a a a a a a a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
425 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 4.2.3. the timing of reflecting the change in the i flag to the interrupt 4.2.1 interrupt enable flag the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. the content is changed when the i flag is changed causes the acceptance of the interrupt request in the following timing: ? when changing the i flag using the reit instruction, the acceptance of the interrupt takes effect as the reit instruction is executed. ? when changing the i flag using one of the fclr, fset, popc, and ldc instructions, the acceptance of the interrupt is effective as the next instruction is executed. 4.2.2 interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). previous instruction reit interrupt sequence time interrupt request generated determination whether or not to accept interrupt request previous instruction fset i interrupt sequence next instruction interrupt request generated determination whether or not to accept interrupt request when changed by reit instruction when changed by fclr, fset, popc, or ldc instruction (if i flag is changed from 0 to 1 by reit instruction) (if i flag is changed from 0 to 1 by fset instruction) time
426 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 4.2.3 interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table 4.2.1 shows the settings of interrupt priority levels and table 4.2.2 shows the interrupt levels en- abled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another. table 4.2.2. interrupt levels enabled according to the contents of the ipl table 4.2.1. settings of interrupt priority levels when either the ipl or the interrupt priority level is changed, the new level is reflected to the interrupt in the following timing: ? when changing the ipl using the reit instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle in volved in the reit instruction. ? when changing the ipl using either the popc, ldc or ldipl instruction, the reflection takes effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the instruction used. ? when changing the interrupt priority level using the mov or similar instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in the instruction used. interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl
427 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 4.2.4 rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue.
428 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 4.3.1 interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 4.3.1 shows the interrupt response time. figure 4.3.1. interrupt response time 4.3 interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16 . (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (4) saves the content of the temporary register (note 1) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) time from interrupt request is generated to when the instruction then under execution is completed. (b) time in which the interrupt sequence is executed.
429 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r interrupt sources without priority levels 7 value set in the ipl watchdog timer other not changed 0 4.3.2 variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 4.3.2 is set in the ipl. table 4.3.2. relationship between interrupts without interrupt priority levels and ipl table 4.3.1. time required for executing the interrupt sequence reset time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 4.3.1. ________ note 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. note 2: locate an interrupt vector address in an even address, if possible. figure 4.3.2. time required for executing the interrupt sequence stack pointer (sp) value interrupt vector address 16-bit bus, without wait 8-bit bus, without wait even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 indeterminate sp-2 sp-4 vec vec+2 pc bclk address bus data bus w r
430 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 4.3.3 saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure 4.3.3 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). figure 4.3.3. state of stack before and after acceptance of interrupt request address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m ?1 m ?2 m ?3 m ?4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ?1 m ?2 m ?3 m ?4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m )
431 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 4.3.4. operation of saving registers the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 4.3.4 shows the operation of the saving registers. note: stack pointer indicated by u flag. (2) stack pointer (sp) contains odd number [sp] (odd) [sp] ?1 (even) [sp] ?2(odd) [sp] ?3 (even) [sp] ?4(odd) [sp] ?5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] ?1(odd) [sp] ?2 (even) [sp] ?3(odd) [sp] ?4 (even) [sp] ?5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h )
432 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 4.5 interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted (see figure 4.5.1). priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure 4.5.2 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. 4.4 returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. return the other registers saved by software within the interrupt routine using the popm or similar instruc- tion before executing the reit instruction.
433 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 4.5.1. maskable interrupts priorities (peripheral i/o interrupts) figure 4.5.2. hardware interrupts priorities ________ reset > dbc > watchdog timer > peripheral i/o > single step > address match timer b2 timer b0 timer a3 timer a1 timer b1 timer a4 timer a2 uart1 reception uart0 reception a-d conversion dma1 timer a0 uart1 transmission uart0 transmission dma0 int1 int2 int0 high low priority of peripheral i/o interrupts (if priority levels are same) int4 int5 int3 si/o2 automatic transfer fld
434 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 4.6 multiple interrupts the state when control branched to an interrupt routine is described below: the interrupt enable flag (i flag) is set to 0 (the interrupt is disabled). the interrupt request bit of the accepted interrupt is set to 0. the processor interrupt priority level (ipl) is assigned to the same interrupt priority level as assigned to the accepted interrupt. setting the interrupt enable flag (i flag) to 1 within an interrupt routine allows an interrupt request assigned a priority higher than the ipl to be accepted. figure 4.6.1 shows the scheme of multiple interrupts. an interrupt request that is not accepted because of low priority will be held. if the condition following is met when the reit instruction returns the ipl and the interrupt priority is determined, then the interrupt request being held is accepted. interrupt priority level of the interrupt request being held > returned the ipl
435 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 4.6.1. multiple interrupts main routine reset i = 0 ipl = 0 i = 1 interrupt 1 i = 0 ipl = 3 i = 1 interrupt 2 i = 0 ipl = 5 reit i = 1 ipl = 3 interrupt 3 reit i = 1 ipl = 0 interrupt 3 i = 0 ipl = 2 reit i = 1 ipl = 0 interrupt 1 interrupt priority level = 3 interrupt 2 interrupt 3 interrupt priority level = 5 interrupt priority level = 2 not acknowledged because of low interrupt priority interrupt request generated nesting time : automatically executed. : be sure to set in software. i : interrupt enable flag ipl : processor interrupt priority level main routine instructions are not executed. multiple interrupts
436 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r ______ figure 4.7.1. switching condition of int interrupt request 4.7 precautions for interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. (3) external interrupt _______ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 _______ through int 5 regardless of the cpu operation clock. ________ ________ ? when the polarity of the int 0 to int 5 pins is changed, the interrupt request bit is sometimes set to 1. after changing the polarity, set the interrupt request bit to 0. figure 4.7.1 shows the procedure for ______ changing the int interrupt generate factor. set the polarity select bit clear the interrupt request bit to ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to ? (disable interrupt) set the interrupt enable flag to ? (enable interrupt)
437 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r (4) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue.
438 interrupt m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r this page kept blank for layout purposes.
chapter 5 standard characteristics
440 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 5.1 standard dc characteristics the standard characteristics given in this section are examples of M30218mc-axxxfp. the contents of these examples cannot be guaranteed. for standardized values, see ?lectric characteristics? 5.1.1 standard ports characteristics figures 5.1.1 through 5.1.6 show the standard ports characteristics.
441 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 5.1.1. i oh - v oh standard characteristics of ports p4 4 to p4 7 , p7 to p10 (v cc = 5v) figure 5.1.2. i ol - v ol standard characteristics of ports p4 4 to p4 7 , p7 to p10 (v cc = 5v) 012345 ?0 ?5 i oh [ma] v oh [v] ta = 90 c ta = ?0 c ta = 25 c v cc = 5 v cmos ports note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values. 012345 50 25 i ol [ma] v ol [v] note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values. ta = 90 c ta = 25 c v cc = 5 v cmos ports ta = ?0 c
442 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 5.1.3. i oh - v oh standard characteristics of ports p4 4 to p4 7 , p7 to p10 (v cc = 3v) figure 5.1.4. i ol - v ol standard characteristics of ports p4 4 to p4 7 , p7 to p10 (v cc = 3v) 0 1.5 3 ?0 ?0 i oh [ma] v oh [v] note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values. ta = 90 c ta = 25 c v cc = 3 v cmos ports ta = ?0 c 0 1.5 3 ?0 ?0 i ol [ma] v ol [v] note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values. ta = 90 c ta = 25 c v cc = 3 v cmos ports ta = ?0 c
443 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figure 5.1.5. i oh - v oh standard characteristics of ports p0 to p3, p4 0 to p4 3 , p5, p6 (v cc = 5v) figure 5.1.6. i ol - v ol standard characteristics of ports p0 to p3, p4 0 to p4 3 , p5, p6 (v cc = 3v) 012345 ?00 ?0 i oh [ma] v oh [v] note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values. ta = 90 c ta = 25 c v cc = 5 v high-breakdown-voltage ports ta = ?0 c 0 1.5 3 ?0 ?5 i oh [ma] v oh [v] note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values. ta = 90 c ta = 25 c v cc = 3 v high-breakdown-voltage ports ta = ?0 c
444 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 5.1.2 characteristics of i cc -f(x in ) figures 5.1.7 and 5.1.8 show the characteristics of i cc -f(x in ). figures 5.1.7. characteristics of i cc -f(x in ) (v cc = 5v) 20 15 10 5 0 024681012 x in / 1 i cc [ma] f(x in ) [mhz] v cc = 5 v 25 ?measurement conditions : v cc = 5v, ta = 25?c, f(x in ) : square waveform input, single-chip mode when access to rom and ram ?register setting condition x in - x out drive capacity select bit = ??(high) main clock (x in - x out ) stop bit = ??(on) x in / 2 x in / 4 x in / 8 x in / 16 note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values.
445 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r figures 5.1.8. characteristics of i cc -f(x in ) (v cc = 3v) 20 15 10 5 0 024681012 i cc [ma] f(x in ) [mhz] ?measurement conditions : v cc = 3v, ta = 25?c, f(x in ) : square waveform input, single-chip mode when access to rom and ram ?register setting condition x in - x out drive capacity select bit = ??(high) main clock (x in - x out ) stop bit = ??(on) v cc = 3 v x in x in / 2 x in / 4 x in / 8 x in / 16 note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values.
446 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 5.2 standard characteristics of a-d converter the standard characteristics given in this section are an example of M30218mc-axxxfp. the contents of these examples cannot be guaranteed. for standardize values, see ?lectric characteristics? figures 5.2.1 and 5.2.2 show the standard characteristics of the a-d converter. the line on the top side of the graph represents absolute errors. the line on the bottom side of the graph represents the width of input voltage bearing the equal output code. note: data described here are characteristic examples. the data values are not guaranteed. refer to section ?lectrical characteristics?for rated values. measurement conditions (v cc = 5.12v, v ref = 5.12v, f(x in ) = 10mhz, ta?c) figure 5.2.1. standard characteristics of the a-d converter -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 0 256 512 768 1024 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 M30218mc with sample & hold, 10 bit characteristics of a-d conversion ad = x in = 10 mhz avcc = vcc = vref = 5.12 v 1 lsb = 5 mv absolute error [lsb] a-d conversion output code absolute error [lsb] (without a quantization error) differential non-linearity error [lsb]
447 standard characteristics figure 5.2.2. standard characteristics of the a-d converter note: data described here are characteristic examples. the data values are not guaranteed. refer to section electrical characteristics for rated values. measurement conditions (v cc = 3.072v, v ref = 3.072v, f(x in ) = 3.5mhz, ta = 25?c) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 64 128 192 256 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 M30218mc 8 bit, characteristics of a-d conversion avcc = vcc = vref = 3.072v 1 lsb = 12 mv f ad = x in /2, x in = 3.5 mhz absolute error [lsb] a-d conversion output code absolute error [lsb] (without a quantization error) differential non-linearity error [lsb]
448 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 5.3 standard characteristics of d-a converter the standard characteristics given in this section are an example of M30218mc-axxxfp. the contents of these examples cannot be guaranteed. for standardized values, see ?lectric characteristics? figures 5.3.1 and 5.3.2 show the standard characteristics of the d-a converter. the line on the bottom side of the graph represents absolute errors. this indicates the difference between the measurement and the ideal analog value corresponding to the input code. the line on the top side of the graph represents the variation width of analog output value corresponding to 1-bit variation in the input code.
449 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r measurement conditions (v cc = 5.12v, v ref = 5.12v, f(x in ) = 10mhz, ta = 25?c) figure 5.3.1. characteristics of the d-a converter note: data described here are characteristic examples. the data values are not guaranteed. refer to section electrical characteristics for rated values. -30 -20 -10 0 10 20 30 0 32 64 96 128 -30 -20 -10 0 10 20 30 M30218mc 8 bit, characteristics of d-a conversion absolute accuracy [mv] 1 lsb width = 20mv absolute accuracy [mv] d-a input code avcc = vcc = vref = 5.12v 1lsb = 20mv x in = 10 mhz -30 -20 -10 0 10 20 30 128 160 192 224 256 -30 -20 -10 0 10 20 30 absolute accuracy [mv] d-a input code
450 standard characteristics measurement conditions (v cc = 3.072v, v ref = 3.072v, f(x in ) = 3.5mhz, ta = 25?c) figure 5.3.2. characteristics of the d-a converter note: data described here are characteristic examples. the data values are not guaranteed. refer to section electrical characteristics for rated values. -50 -40 -30 -20 -10 0 10 20 30 40 50 0 32 64 96 128 -50 -40 -30 -20 -10 0 10 20 30 40 50 M30218fc/mc 8 bit, characteristics of d-a conversion absolute accuracy [mv] 1 lsb width = 20mv absolute accuracy [mv] d-a input code avcc = vcc = vref = 3.072v 1lsb = 12mv x in = 3.5 mhz -50 -40 -30 -20 -10 0 10 20 30 40 50 128 160 192 224 256 -50 -40 -30 -20 -10 0 10 20 30 40 50 absolute accuracy [mv] d-a input code
451 standard characteristics m i t s u b i s h i m i c r o c o m p u t e r s m 3 0 2 1 8 g r o u p s i n g l e - c h i p 1 6 - b i t c m o s m i c r o c o m p u t e r 5.4 standard characteristics of pull-up resistor figure 5.4.1 shows an example of the standard characteristics of the pull-up resistor. figure 5.4.1. example of the standard characteristics of the pull-up resistor 5.0 ?00.0 v i (v) 0 1.0 2.0 3.0 4.0 ?0.0 ?00.0 ?60.0 i i ( m a) vcc = 5 v note: data described here are characteristic examples. the data values are not guaranteed. vcc = 3 v
mitsubishi semiconductors user? manual M30218 group rev.b jun. 2001 editioned by committee of editing of mitsubishi semiconductor user? manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?001 mitsubishi electric corporation
user s manual M30218 group
rev. rev. no. date a first edition 991125 a1 the followings are updated: 991221 page 56 figure 39: fldc mode register b3b2 (at rising edge of each digit) 10 : 2 x tdisp page 447 figure 5.2.2, page 450 figure 5.3.2 : measurement conditions....f(x in )= 3.5mhz b the followings are updated: 010627 pages 3, 6, 7, 8, 9, 129, 134, 135, 141, 143, 147, 286, 440, 446, and 448: delete about mask option specification of pull-down resistor page 151 table 71 automatic transfer serial i/o: decided electrical standard values (at v cc = 3 v) page 154 figure 125 block diagram of flash memory version: user rom area block number e0000 16 to e7fff 16 block 0 ---> block 3 e8000 16 to effff 16 block 1 ---> block 2 f0000 16 to f7fff 16 block 2 ---> block 1 f8000 16 to fffff 16 block 3 ---> block 0 page 155 figure 126 flash memory control register bit6 bit5 bit4 000: block 0 program/erase ---> block 3 program/erase 001: block 1 program/erase ---> block 2 program/erase 010: block 2 program/erase ---> block 1 program/erase 011: block 3 program/erase ---> block 0 program/erase page 225 2.3.7 precautions for timer b (pulse period/pulse width measurement mode) line 7 ....this flag cannot be set to ??by.... ---> ....this flag can be set to ??by.... revision description list M30218 group user? manual (1/1) revision description

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